AT86RF212 Atmel Corporation, AT86RF212 Datasheet - Page 18

• Manufacturer Part Number: AT86RF212
• Manufacturer: Atmel Corporation

Specifications of AT86RF212

• Max. Operating Frequency: 0 MHz
• Crypto Engine: AES
• Operating Voltage (vcc): 1.8 to 3.6
• Frequency Band: 700/800/900MHz
• Max Data Rate (mb/s): 1
• Antenna Diversity: No
• External Pa Control: Yes
• Power Output (dbm): 10
• Receiver Sensitivity (dbm): -110
• Receive Current Consumption (ma): 9.0
• Transmit Current Consumption (ma): 18 at 5dBm
• Link Budget (dbm): 120

Figure 4-8. Packet Structure - Frame Write Access
Figure 4-9. Exemplary SPI Sequence - Frame Buffer Read of a Frame with 2-byte PSDU
18
AT86RF212
Table 4-3. RX_STATUS
Note, the Frame Buffer read access can be terminated at any time without any
consequences by setting /SEL = H, e.g. after reading the frame length byte only. A
successive Frame Buffer read operation starts again at the PHR field.
On Frame Buffer write access, the second byte transferred on MOSI contains the frame
length (PHR field) followed by the payload data (PSDU) as shown in Figure 4-8.
The number of bytes n for one frame buffer access is calculated as follows:
Read Access: n = 5 + frame_length
Write Access: n = 2 + frame_length
The maximum value of frame_length is 127 bytes. That means that n ≤ 132 for Frame
Buffer read and n ≤ 129 for Frame Buffer write accesses.
Each read or write of a data byte automatically increments the address counter of the
Frame Buffer until the access is terminated by setting /SEL = H.
Figure 4-9 and Figure 4-10 illustrate an exemplary SPI sequence of a Frame Buffer
access to read a frame with 2-byte PSDU and write a frame with 4-byte PSDU.
Bit
Content
Reference
7
RX_CRC_VALID
(register 0x06, PHY_RSSI)
Section 6.3.5
[PHY_STATUS, PHR, PSDU data, LQI, ED, and RX_STATUS]
[command byte, PHR, and PSDU data]
6
TRAC_STATUS
(register 0x02, TRX_STATE)
Section 5.2.6
5
4
8168C-MCU Wireless-02/10
3 … 0
Reserved