AT86RF212 Atmel Corporation, AT86RF212 Datasheet - Page 95

• Manufacturer Part Number: AT86RF212
• Manufacturer: Atmel Corporation

Specifications of AT86RF212

• Max. Operating Frequency: 0 MHz
• Crypto Engine: AES
• Operating Voltage (vcc): 1.8 to 3.6
• Frequency Band: 700/800/900MHz
• Max Data Rate (mb/s): 1
• Antenna Diversity: No
• External Pa Control: Yes
• Power Output (dbm): 10
• Receiver Sensitivity (dbm): -110
• Receive Current Consumption (ma): 9.0
• Transmit Current Consumption (ma): 18 at 5dBm
• Link Budget (dbm): 120

7.1.5 Register Description
8168C-MCU Wireless-02/10
Scrambler
For data rates 1000 kbit/s and 400 kbit/s, additional chip scrambling is applied per
default in order to mitigate data dependent spectral properties. Scrambling can be
disabled if bit OQPSK_SCRAM_EN (register 0x0C, TRX_CTRL_2) is set to 0.
Energy Detection
The ED measurement time span is 8 symbol periods according to IEEE 802.15.4. For
frames operated at a higher data rate, the automated measurement duration (see
section 6.5.2) is reduced to 2 symbol periods taking reduced frame durations into
account. This means, the ED measurement time is 80 µs for modes 200 kbit/s and 400
kbit/s, and 32 µs for modes 500 kbit/s and 1000 kbit/s. For manually initiated ED
measurements in these modes, the measurement time is still 8 symbol periods.
Carrier Sense
For clear channel assessment, IEEE 802.15.4-2006 specifies several modes which may
either apply “energy above threshold” or “carrier sense” (CS) or a combination of both.
Since signals of the High Data Rate Modes are not compliant to IEEE 802.15.4-2006,
CS is not supported when the AT86RF212 is operating in these modes. However,
“energy above threshold” is supported.
Link Quality Indicator (LQI)
For the High Data Rate Modes, the link quality value does not contain useful
information and should be discarded.
Register 0x0C (TRX_CTRL_2):
The TRX_CTRL_2 register controls the PHY mode settings. Note that during
configuration, the transceiver needs to be in state TRX_OFF.
Table 7-3. Register 0x0C (TRX_CTRL_2)
• Bit 7 – RX_SAFE_MODE
Refer to section 9.7.2.
• Bit 6 – TRX_OFF_AVDD_EN
Refer to sections 5.1.4.3 and 7.5.4.
Bit
Name
Read/Write
Reset Value
Bit
Name
Read/Write
Reset Value
7
RX_SAFE_MODE
R/W
0
3
BPSK_OQPSK
R/W
0
6
TRX_OFF_AVDD_EN
R/W
0
2
SUB_MODE
R/W
1
5
OQPSK_SCRAM_EN
R/W
1
1
OQPSK_DATA_RATE
R/W
0
AT86RF212
4
OQPSK_SUB1_RC_EN
R/W
0
0
OQPSK_DATA_RATE
R/W
0
95