AT86RF212 Atmel Corporation, AT86RF212 Datasheet - Page 5

• Manufacturer Part Number: AT86RF212
• Manufacturer: Atmel Corporation

Specifications of AT86RF212

• Max. Operating Frequency: 0 MHz
• Crypto Engine: AES
• Operating Voltage (vcc): 1.8 to 3.6
• Frequency Band: 700/800/900MHz
• Max Data Rate (mb/s): 1
• Antenna Diversity: No
• External Pa Control: Yes
• Power Output (dbm): 10
• Receiver Sensitivity (dbm): -110
• Receive Current Consumption (ma): 9.0
• Transmit Current Consumption (ma): 18 at 5dBm
• Link Budget (dbm): 120

2.2.1 Analog and RF Pins
2.2.1.1 Supply and Ground Pins
8168C-MCU Wireless-02/10
Paddle
Pin
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Name
DIG2
SLP_TR
DVSS
DVDD
DVDD
DEVDD
DVSS
CLKM
DVSS
SCLK
MISO
DVSS
MOSI
/SEL
IRQ
XTAL2
XTAL1
AVSS
EVDD
AVDD
AVSS
AVSS
AVSS
AVSS
Type
Digital output
Digital input
Ground
Analog
Analog
Supply
Ground
Digital output
Ground
Digital input
Digital output
Ground
Digital input
Digital input
Digital output
Analog
Analog
Ground
Supply
Analog
Ground
Ground
Ground
Ground
EVDD, DEVDD
EVDD and DEVDD are analog and digital supply voltage pins of the AT86RF212 radio
transceiver.
AVDD, DVDD
AVDD and DVDD are outputs of the internal voltage regulators and require bypass
capacitors for stable operation. The voltage regulators are controlled independently by
the radio transceivers state machine and are activated depending on the current radio
transceiver state. The voltage regulators can be configured for external supply; for
details, refer to section 7.5.
AVSS, DVSS
AVSS and DVSS are analog and digital ground pins respectively.
Description
1. General purpose signal (inverted DIG1), see section 9.3
2. Signal IRQ_2 (RX_START) for RX Frame Time Stamping, see section 9.5
If disabled, internally pulled to DVSS
Controls sleep, transmit start, and receive states; active high; see section 4.6
Digital ground
Regulated 1.8 V internal supply voltage; digital domain; see section 7.5
Regulated 1.8 V internal supply voltage; digital domain; see section 7.5
External supply voltage; digital domain
Digital ground
Master clock signal output; low if disabled; see section 7.7
Digital ground
SPI clock
SPI data output (master input slave output)
Digital ground
SPI data input (master output slave input)
SPI select; active low
1. Interrupt request signal; active high or active low; see section 4.7
2. Buffer-level mode indicator; active high
Crystal pin, see sections 2.2.1.3 and 7.7
Crystal pin or external clock supply, see sections 2.2.1.3 and 7.7
Analog ground
External supply voltage; analog domain
Regulated 1.8 V internal supply voltage; analog domain; see section 7.5
Analog ground
Analog ground
Analog ground
Analog ground; exposed paddle of QFN package
AT86RF212
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