AT86RF212 Atmel Corporation, AT86RF212 Datasheet - Page 39

• Manufacturer Part Number: AT86RF212
• Manufacturer: Atmel Corporation

Specifications of AT86RF212

• Max. Operating Frequency: 0 MHz
• Crypto Engine: AES
• Operating Voltage (vcc): 1.8 to 3.6
• Frequency Band: 700/800/900MHz
• Max Data Rate (mb/s): 1
• Antenna Diversity: No
• External Pa Control: Yes
• Power Output (dbm): 10
• Receiver Sensitivity (dbm): -110
• Receive Current Consumption (ma): 9.0
• Transmit Current Consumption (ma): 18 at 5dBm
• Link Budget (dbm): 120

Table 5-2. Analog Block Initialization and Settling Times
8168C-MCU Wireless-02/10
No.
Symbol Block
10
11
12
13
14
5
6
7
8
9
t
t
t
t
t
t
t
t
t
t
t
t
t
TR15
TR16
TR17
TR18
TR19
TR20
TR21
TR22
TR23
TR24
TR25
TR26
TR28
Symbol
t
t
t
t
t
t
t
t
t
t
TR10
TR11
TR12
TR13
TR14
TR5
TR6
TR7
TR8
TR9
XOSC
FTN
DVREG
AVREG
PLL, initial
PLL, settling
PLL, CF cal.
PLL, DCU cal.
PLL, RX
PLL, TX
RSSI
ED
CCA
PLL_ON
TRX_OFF
RX_ON
PLL_ON
RX_ON
PLL_ON
BUSY_TX
All states
RESET
Various
states
RX
TX
Transition
Time, typ.
330 µs
150 µs
150 µs
200 µs
11 µs
8 µs
TRX_OFF
RX_ON
TRX_OFF
RX_ON
PLL_ON
BUSY_TX
PLL_ON
TRX_OFF
TRX_OFF
PLL_ON
The state transition timing is calculated based on the timing of the individual blocks
shown in Figure 5-3 to Figure 5-7. The worst case values include maximum operating
temperature, minimum supply voltage, and device parameter variations, see Table 5-2.
8 symbol periods
8 symbol periods
BPSK-20: 32 µs
BPSK-40: 24 µs
O-QPSK: 8 µs
10 µs
16 µs
32 µs
1 symbol period When asserting pin 11 (SLP_TR) or TRX_CMD = TX_START, first
Time, max.
1000 µs
1500 µs
1500 µs
Time, typ.
370 µs
270 µs
25 µs
42 µs
200 µs
32 µs
26 µs
1 µs
1 µs
1 µs
1 µs
1 µs
1 µs
Comments
Leaving SLEEP state; depends on crystal oscillator setup (Siward
A207-011, C
Filter tuning time
Depends on external bypass capacitor at DVDD (CB3 = 1 µF nom.,
10 µF worst case), and on V
Depends on external bypass capacitor at AVDD (CB1 = 1 µF nom.,
10 µF worst case) , and on V
PLL settling time TRX_OFF
settling time (see t
Duration of a channel switch within frequency band, refer to section
7.8.3
PLL center frequency calibration, refer to section 7.8.4
PLL DCU calibration, refer to section 7.8.4
PLL settling time, refer to section 7.8.3
PLL settling time, refer to section 7.8.3
RSSI update period in receive states, refer to section 6.4.2
ED measurement period; different timing with High Data Rate
Modes, see sections 6.5.2 and 7.1.4.3
CCA measurement period, refer to section 6.6.2
Comments
Depends on external capacitor at AVDD (CB1 = 1 µF nom.);
register bit TRX_OFF_AVDD_EN (register 0x0c, TRX_CTRL_2) is
not set; for details, refer to section 7.8.3
Transition time is also valid for TX_ARET_ON / RX_AACK_ON
PLL_ON
symbol transmission is delayed by 1 symbol period (PLL settling
and PA ramp up)
Using TRX_CMD = FORCE_TRX_OFF (see register 0x02,
TRX_STATE); not valid for SLEEP
Using TRX_CMD = FORCE_PLL_ON (see register 0x02,
TRX_STATE); not valid for states SLEEP, P_ON, RESET,
TRX_OFF, and *_NOCLK
PLL settling time, refer to section 7.8.3
Not valid for reset in states P_ON or SLEEP
L
= 10 pF)
TR18
)
DD
DD
PLL_ON, including 150 µs AVREG
TRX_OFF (see t
AT86RF212
TR2
)
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