AT86RF212 Atmel Corporation, AT86RF212 Datasheet - Page 133

• Manufacturer Part Number: AT86RF212
• Manufacturer: Atmel Corporation

Specifications of AT86RF212

• Max. Operating Frequency: 0 MHz
• Crypto Engine: AES
• Operating Voltage (vcc): 1.8 to 3.6
• Frequency Band: 700/800/900MHz
• Max Data Rate (mb/s): 1
• Antenna Diversity: No
• External Pa Control: Yes
• Power Output (dbm): 10
• Receiver Sensitivity (dbm): -110
• Receive Current Consumption (ma): 9.0
• Transmit Current Consumption (ma): 18 at 5dBm
• Link Budget (dbm): 120

9.1.3 Security Key Setup
9.1.4 Security Operation Modes
9.1.4.1 Electronic Code Book (ECB)
8168C-MCU Wireless-02/10
The AES module control registers are only accessible using SRAM read and write
accesses on address space 0x82 to 0x94. Configuring the AES mode, providing the
data, and starting a decryption or encryption operation can be combined in a single
SRAM access.
Notes
• No additional register access is required to operate the security block.
• Using AES in TRX_OFF state requires an activated clock at pin 17 (CLKM), i.e.
• Access to the security block is not possible while the radio transceiver is in state
• All configurations of the security module, the SRAM content, and keys are reset
• A read or write access to register 0x83 (AES_CTRL) during AES operation
The setup of the key is prepared by setting register bits AES_MODE = 0x1 (SRAM
address 0x83, AES_CTRL). Afterwards, the 128 bit key must be written to SRAM
addresses 0x84 through 0x93 (registers AES_KEY). It is recommended to combine the
setting of control register 0x83 (AES_CTRL) and the 128 bit key transfer using only one
SRAM access starting from address 0x83.
The address space of the 128-bit key and 128-bit data is identical from a programming
point of view. However, both use different pages which are selected by register bit
AES_MODE before storing the data.
A read access to registers AES_KEY (0x84 – 0x93) returns the last round key of the
preceding security operation. After an ECB encryption operation, this is the key that is
required for the corresponding ECB decryption operation. However, the initial AES key,
written to the security module in advance of an AES run (see step 1 in Table 9-1), is not
modified during an AES operation. This initial key is used for the next AES run, even it
cannot be read from AES_KEY.
Note
• ECB decryption is not required for IEEE 802.15.4 or ZigBee security processing. The
ECB is the basic operating mode of the security module. After setting up the initial AES
key, register bits AES_MODE = 0 (SRAM address 0x83, AES_CTRL) set up the ECB
mode. Register bit AES_DIR (SRAM address 0x83, AES_CTRL) selects the direction,
either encryption or decryption. The data to be processed has to be written to SRAM
addresses 0x84 through 0x93 (registers AES_STATE).
An example for a programming sequence is shown in Figure 9-1. This example
assumes that a suitable key has been loaded before.
A security operation can be started within one SRAM access by appending the start
command AES_REQUEST = 1 (register 0x94, AES_CTRL_MIRROR) to the SPI
register bits CLKM_CTRL ≠ 0. For further details, refer to section 7.7.4.
SLEEP.
during SLEEP or RESET states.
terminates the current processing.
AT86RF212 provides this functionality as an additional feature.
AT86RF212
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