AT86RF212 Atmel Corporation, AT86RF212 Datasheet - Page 33

• Manufacturer Part Number: AT86RF212
• Manufacturer: Atmel Corporation

Specifications of AT86RF212

• Max. Operating Frequency: 0 MHz
• Crypto Engine: AES
• Operating Voltage (vcc): 1.8 to 3.6
• Frequency Band: 700/800/900MHz
• Max Data Rate (mb/s): 1
• Antenna Diversity: No
• External Pa Control: Yes
• Power Output (dbm): 10
• Receiver Sensitivity (dbm): -110
• Receive Current Consumption (ma): 9.0
• Transmit Current Consumption (ma): 18 at 5dBm
• Link Budget (dbm): 120

5.1.2.4 PLL_ON – PLL State
5.1.2.5 RX_ON and BUSY_RX – RX Listen and Receive State
5.1.2.6 RX_ON_NOCLK – RX Listen State without CLKM
8168C-MCU Wireless-02/10
Entering the PLL_ON state from TRX_OFF state enables the analog voltage regulator
(AVREG) first, unless the AVREG is already switched on (register 0x0C,
TRX_OFF_AVDD_EN). After the voltage regulator has been settled (see Table 5-2), the
PLL frequency synthesizer is enabled. When the PLL has been settled at the receive
frequency to a channel defined by register bits CHANNEL (register 0x08,
PHY_CC_CCA), CC_NUMBER (register 0x013, CC_CTRL_0), and CC_BAND (register
0x014, CC_CTRL_1), a successful PLL lock is indicated by issuing an interrupt IRQ_0
(PLL_LOCK).
After the RX_ON command is issued in PLL_ON state, register bits TRX_STATUS
(register 0x01, TRX_STATUS) immediately indicate the radio being in RX_ON state.
However, frame reception can only start, once the PLL has locked.
The PLL_ON state corresponds to the TX_ON state in IEEE 802.15.4.
The AT86RF212 receive mode is internally separated into RX_ON state and BUSY_RX
state. There is no difference between these states with respect to the analog radio
transceiver circuitry, which is always turned on. In both states the receiver and the PLL
frequency synthesizer are enabled.
During RX_ON state, the receiver listens for incoming frames. After detecting a valid
synchronization header (SHR), the AT86RF212 automatically enters the BUSY_RX
state. The reception of a non-zero PHR field generates an IRQ_2 (RX_START) if
enabled.
During PSDU reception, the frame data are stored continuously in the Frame Buffer
until the last byte was received. The completion of the frame reception is indicated by
an interrupt IRQ_3 (TRX_END) and the radio transceiver returns to state RX_ON. At
the same time, the register bit RX_CRC_VALID (register 0x06, PHY_RSSI) is updated
with the result of the FCS check (see section 6.3).
Received frames are passed to the address match filter, refer to section 6.2. If the
content of the MAC addressing fields (refer to IEEE 802.15.4-2006, section 7.2.1) of a
frame matches to the expected addresses, which is further dependent on the
addressing mode, an address match interrupt IRQ_5 (AMI) is issued. The expected
address values are to be stored in registers 0x20 – 0x2B (Short address, PAN ID, and
IEEE address). Frame filtering is available in Basic and Extended Operating Mode,
refer to section 6.2.
Leaving state RX_ON is only possible by writing a state change command to register
bits TRX_CMD in register 0x02 (TRX_STATE).
If the radio transceiver is listening for an incoming frame and the microcontroller is not
running an application, the microcontroller may be powered down to decrease the total
system power consumption. This specific power-down scenario – for systems running in
clock synchronous mode (see section 4) – is supported by the AT86RF212 using the
state RX_ON_NOCLK.
This state can only be entered by setting pin 11 (SLP_TR) = H while the radio
transceiver is in RX_ON state. Pin 17 (CLKM) is disabled 35 clock cycles after the rising
edge at the SLP_TR pin, see Figure 4-16. This allows the microcontroller to complete
its power-down sequence.
AT86RF212
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