AT86RF212 Atmel Corporation, AT86RF212 Datasheet - Page 135

• Manufacturer Part Number: AT86RF212
• Manufacturer: Atmel Corporation

Specifications of AT86RF212

• Max. Operating Frequency: 0 MHz
• Crypto Engine: AES
• Operating Voltage (vcc): 1.8 to 3.6
• Frequency Band: 700/800/900MHz
• Max Data Rate (mb/s): 1
• Antenna Diversity: No
• External Pa Control: Yes
• Power Output (dbm): 10
• Receiver Sensitivity (dbm): -110
• Receive Current Consumption (ma): 9.0
• Transmit Current Consumption (ma): 18 at 5dBm
• Link Budget (dbm): 120

AT86RF212
When decrypting, due to the nature of AES algorithm, the initial key to be used is not
the same as the one used for encryption, but rather the last round key instead. This last
round key is the content of the key address space stored after running one full
encryption cycle and must be saved for decryption. If the decryption key has not been
saved, it has to be recomputed by first running a dummy encryption (of an arbitrary
plaintext) using the original encryption key, then fetching the resulting round key from
the key memory, and writing it back into the key memory as the decryption key.
ECB decryption is not used by either IEEE 802.15.4 or ZigBee frame security. Both of
these standards do not directly encrypt the payload, but rather a nonce instead, and
protect the payload by applying an XOR operation between the resulting (AES-) cipher
text and the original payload. As the nonce is the same for encryption and decryption,
only ECB encryption is required. Decryption is performed by XORing the received
cipher text with its own encryption result, which results in the original plaintext payload
upon success.
9.1.4.2 Cipher Block Chaining (CBC)
In CBC mode, the result of a previous AES operation is XORed with the new incoming
vector forming the new plaintext to encrypt, see Figure 9-4. This mode is used for the
computation of a cryptographic checksum (message integrity code, MIC).
Figure 9-4. CBC Mode - Encryption
After preparing the AES key and defining the AES operation direction using SRAM
register bit AES_DIR, the data has to be provided to the AES engine and the CBC
operation can be started.
The first CBC run has to be configured as ECB to process the initial data (plaintext
XORed with an initialization vector provided by the microcontroller). All succeeding AES
runs are to be configured as CBC by setting register bits AES_MODE = 0x2 (register
0x83, AES_CTRL). Register bit AES_DIR (register 0x83, AES_CTRL) must be set to
AES_DIR = 0 to enable AES encryption. The data to be processed has to be
transferred to the SRAM starting with address 0x84 to 0x93 (register AES_STATE).
Setting register bit AES_REQUEST = 1 (register 0x94, AES_CTRL_MIRROR), as
described in section 9.1.4, starts the first encryption within one SRAM access. This
causes the next 128 bits of plaintext data to be XORed with the previous cipher text
data, see Figure 9-4.
According to IEEE 802.15.4, the input for the very first CBC operation has to be
prepared by XORing a plaintext with an initialization vector (IV). The value of the
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