AT86RF212 Atmel Corporation, AT86RF212 Datasheet - Page 15

• Manufacturer Part Number: AT86RF212
• Manufacturer: Atmel Corporation

Specifications of AT86RF212

• Max. Operating Frequency: 0 MHz
• Crypto Engine: AES
• Operating Voltage (vcc): 1.8 to 3.6
• Frequency Band: 700/800/900MHz
• Max Data Rate (mb/s): 1
• Antenna Diversity: No
• External Pa Control: Yes
• Power Output (dbm): 10
• Receiver Sensitivity (dbm): -110
• Receive Current Consumption (ma): 9.0
• Transmit Current Consumption (ma): 18 at 5dBm
• Link Budget (dbm): 120

4.2 SPI Timing Description
Figure 4-2. SPI Timing: Global Map and Definition of Timing Parameters t
Figure 4-3. SPI Timing: Detailed Drawing of Timing Parameter t
8168C-MCU Wireless-02/10
Pin 17 (CLKM) can be used as a microcontroller master clock source. If the
microcontroller derives the SPI master clock (SCLK) directly from CLKM, the SPI
operates in synchronous mode, otherwise in asynchronous mode.
In synchronous mode, the maximum SCLK frequency is 8 MHz.
In asynchronous mode, the maximum SCLK frequency is limited to 7.5 MHz. The signal
at pin CLKM is not required to derive SCLK and may be disabled to reduce power
consumption and spurious emissions.
Figure 4-2 and Figure 4-3 illustrate the SPI timing and introduces its parameters. The
corresponding timing parameter definitions t
The SPI is based on a byte-oriented protocol and is always a bidirectional
communication between master and slave. The SPI master starts the transfer by
asserting /SEL = L. Then the master generates eight SPI clock cycles to transfer one
byte to the radio transceiver (via MOSI). At the same time, the slave transmits one byte
to the master (via MISO). When the master wants to receive one byte of data from the
slave, it must also transmit one byte to the slave. All bytes are transferred with MSB
first. An SPI transaction is finished by releasing /SEL = H.
/SEL = L enables the MISO output driver of the AT86RF212. The MSB of MISO is valid
after t
SCLK. If the driver is disabled, there is no internal pull-up resistor connected to it.
Driving the appropriate signal level must be ensured by the master device or an
external pull-up resistor. Note, when both /SEL and /RST are active, the MISO output
driver is also enabled.
1
(see section 10.4, parameter 10.4.3) and is updated at each falling edge of
1
, t
2
, t
3
, and t
5
, t
6
4
, t
1
– t
8
, and t
9
are defined in section 10.4.
9
AT86RF212
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