MPC8572DS Freescale Semiconductor, MPC8572DS Datasheet - Page 109

• Manufacturer Part Number: MPC8572DS
• Description: KIT MPU POWERQUICC III
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8572DS

• Contents: Board
• Data Rate: 10 Mbps to 100 Mbps
• Memory Type: Flash, DDR, DDR2, DDR3, SDRAM
• Interface Type: I2C, Ethernet
• Operating Voltage: 3.3 V
• Data Bus Width: 32 bit
• Product: Development Tools
• Silicon Manufacturer: Freescale
• Core Architecture: Power Architecture
• Core Sub-architecture: PowerQUICC
• Silicon Core Number: MPC85xx
• Silicon Family Name: PowerQUICC III
• Rohs Compliant: Yes
• For Use With/related Products: MPC8572E
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Freescale Semiconductor
SD2_TX[0]
SD2_TX[3:0]
SD2_PLL_TPD
SD2_REF_CLK
SD2_REF_CLK
Reserved
GPINOUT[0:7]
HRESET
HRESET_REQ
SRESET
CKSTP_IN0
CKSTP_IN1
CKSTP_OUT0
CKSTP_OUT1
TRIG_IN
TRIG_OUT/READY_P0/QUIES
CE
READY_P1
MSRCID[0:1]
MSRCID[2:4]
MDVAL
CLK_OUT
RTC
SYSCLK
Signal
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
SGMII Tx Data eTSEC1
Transmit Data (negative)
PLL Test Point Digital
PLL Reference Clock
PLL Reference Clock
Complement
General Purpose Input / Output B27, A28, B31, A32,
Hard Reset
Hard Reset Request
Soft Reset
Checkstop In Processor 0
Checkstop In Processor 1
Checkstop Out Processor 0
Checkstop Out Processor 1
Trigger In
Trigger Out / Ready Processor
0/ Quiesce
Ready Processor 1
Memory Debug Source Port ID
Memory Debug Source Port ID
Memory Debug Data Valid
Clock Out
Real Time Clock
System Clock
Table 76. MPC8572E Pinout Listing (continued)
Signal Name
General-Purpose Input/Output
—
System Control
Debug
Clock
AH27, AG25, AE25,
AH32
AG32
AD26
AD27
AG31
AF26, AF27
B30, A31, B28, B29
AC31
L23
P24
N26
N25
U29
T25
P26
P25
N28
U27, T29
U28, W24, W28
V26
U32
V25
Y32
Package Pin Number
Pin Type
I/O
—
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
XV
XV
XV
XV
XV
Supply
Power
Package Description
BV
OV
OV
OV
OV
OV
OV
OV
OV
OV
OV
OV
OV
OV
OV
OV
OV
DS2
DS2
DS2
DS2
DS2
DD_SR
DD_SR
DD_SR
DD_SR
DD_SR
—
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
5, 9, 30
Notes
2, 21
2, 4
2, 4
5, 9
17
28
21
21
21
11
—
—
—
—
—
—
—
—
—
—
—
—
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