MPC8572DS Freescale Semiconductor, MPC8572DS Datasheet - Page 66

• Manufacturer Part Number: MPC8572DS
• Description: KIT MPU POWERQUICC III
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8572DS

• Contents: Board
• Data Rate: 10 Mbps to 100 Mbps
• Memory Type: Flash, DDR, DDR2, DDR3, SDRAM
• Interface Type: I2C, Ethernet
• Operating Voltage: 3.3 V
• Data Bus Width: 32 bit
• Product: Development Tools
• Silicon Manufacturer: Freescale
• Core Architecture: Power Architecture
• Core Sub-architecture: PowerQUICC
• Silicon Core Number: MPC85xx
• Silicon Family Name: PowerQUICC III
• Rohs Compliant: Yes
• For Use With/related Products: MPC8572E
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

At recommended operating conditions with OV
JTAG
Figure 36
Figure 37
Figure 38
66
JTAG external clock to output high impedance:
Notes:
1. All outputs are measured from the midpoint voltage of the falling/rising edge of t
2. The symbols used for timing specifications herein follow the pattern of t
3. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.
4. Non-JTAG signal input timing with respect to t
5. Non-JTAG signal output timing with respect to t
6. Guaranteed by design.
The output timings are measured at the pins. All output timings assume a purely resistive 50-Ω load (see
Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.
for inputs and t
device timing (JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the t
(K) going to the high (H) state or setup time. Also, t
signals (D) went invalid (X) relative to the t
reference symbol representation is based on three letters representing the clock of a particular functional. For rise and fall
times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
provides the AC test load for TDO and the boundary-scan outputs.
provides the JTAG clock input timing diagram.
provides the TRST timing diagram.
Table 53. JTAG AC Timing Specifications (Independent of SYSCLK)
External Clock
(first two letters of functional block)(reference)(state)(signal)(state)
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
TRST
Parameter
JTAG
Output
Boundary-scan data
Figure 36. AC Test Load for the JTAG Interface
Figure 37. JTAG Clock Input Timing Diagram
VM
t
DD
JTKHKL
of 3.3 V ± 5%.
Figure 38. TRST Timing Diagram
JTG
VM
Z
VM = Midpoint Voltage (OV DD /2)
VM = Midpoint Voltage (OV DD /2)
0
TDO
TCLK
clock reference (K) going to the high (H) state. Note that, in general, the clock
t
TCLK
= 50 Ω
JTG
.
JTDXKH
VM
.
t
Symbol
TRST
t
t
JTKLDZ
JTKLOZ
symbolizes JTAG timing (JT) with respect to the time data input
2
VM
for outputs. For example, t
(first two letters of functional block)(signal)(state) (reference)(state)
Min
3
3
R
VM
L
= 50 Ω
TCLK
t
JTGR
to the midpoint of the signal in question.
Max
19
9
OV
DD
t
1
JTGF
/2
JTDVKH
(continued)
Freescale Semiconductor
Unit
ns
symbolizes JTAG
JTG
Figure
clock reference
36).
Notes
5, 6