MPC8572DS Freescale Semiconductor, MPC8572DS Datasheet - Page 90

• Manufacturer Part Number: MPC8572DS
• Description: KIT MPU POWERQUICC III
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8572DS

• Contents: Board
• Data Rate: 10 Mbps to 100 Mbps
• Memory Type: Flash, DDR, DDR2, DDR3, SDRAM
• Interface Type: I2C, Ethernet
• Operating Voltage: 3.3 V
• Data Bus Width: 32 bit
• Product: Development Tools
• Silicon Manufacturer: Freescale
• Core Architecture: Power Architecture
• Core Sub-architecture: PowerQUICC
• Silicon Core Number: MPC85xx
• Silicon Family Name: PowerQUICC III
• Rohs Compliant: Yes
• For Use With/related Products: MPC8572E
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Serial RapidIO
17.1
For more information, see
17.2
Figure
17.3
With the use of high speed serial links, the interconnect media causes degradation of the signal at the
receiver. Effects such as Inter-Symbol Interference (ISI) or data dependent jitter are produced. This loss
can be large enough to degrade the eye opening at the receiver beyond what is allowed in the specification.
To negate a portion of these effects, equalization can be used. The most common equalization techniques
that can be used are as follows:
17.4
AC electrical specifications are given for transmitter and receiver. Long run and short run interfaces at
three baud rates (a total of six cases) are described.
The parameters for the AC electrical specifications are guided by the XAUI electrical interface specified
in Clause 47 of IEEE 802.3ae-2002.
XAUI has similar application goals to serial RapidIO, as described in
Ethernet Controller (eTSEC) (10/100/1000 Mbps)—FIFO/GMII/MII/TBI/RGMII/RTBI/RMII Electrical
Characteristics.” The goal of this standard is that electrical designs for Serial RapidIO can reuse electrical
designs for XAUI, suitably modified for applications at the baud intervals and reaches described herein.
90
Symbol
t
t
REFCJ
REFPJ
t
REF
•
•
64lists the AC requirements.
A passive high pass filter network placed at the receiver. This is often referred to as passive
equalization.
The use of active circuits in the receiver. This is often referred to as adaptive equalization.
REFCLK cycle time
REFCLK cycle-to-cycle jitter. Difference in
the period of any two adjacent REFCLK
cycles
Phase jitter. Deviation in edge location with
respect to mean edge location
DC Requirements for Serial RapidIO SD1_REF_CLK and
Explanatory Note on Transmitter and Receiver Specifications
SD1_REF_CLK
AC Requirements for Serial RapidIO SD1_REF_CLK and
SD1_REF_CLK
Equalization
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Parameter Description
Table 64. SD n _REF_CLK and SD n _REF_CLK AC Requirements
Section 15.2, “SerDes Reference Clocks.”
Min
–40
—
—
Typical Max Units
10(8)
—
—
80
40
—
Section 8.1, “Enhanced Three-Speed
ns
ps
ps
with 125-MHz reference clock
8 ns applies only to serial RapidIO
Freescale Semiconductor
Comments
—
—