MPC8572DS Freescale Semiconductor, MPC8572DS Datasheet - Page 35

• Manufacturer Part Number: MPC8572DS
• Description: KIT MPU POWERQUICC III
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8572DS

• Contents: Board
• Data Rate: 10 Mbps to 100 Mbps
• Memory Type: Flash, DDR, DDR2, DDR3, SDRAM
• Interface Type: I2C, Ethernet
• Operating Voltage: 3.3 V
• Data Bus Width: 32 bit
• Product: Development Tools
• Silicon Manufacturer: Freescale
• Core Architecture: Power Architecture
• Core Sub-architecture: PowerQUICC
• Silicon Core Number: MPC85xx
• Silicon Family Name: PowerQUICC III
• Rohs Compliant: Yes
• For Use With/related Products: MPC8572E
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

At recommended operating conditions with LV
Figure 12
8.2.3.2
Table 30
Figure 13
Freescale Semiconductor
RX_CLK clock period 10 Mbps
RX_CLK clock period 100 Mbps
RX_CLK duty cycle
RXD[3:0], RX_DV, RX_ER setup time to RX_CLK
RXD[3:0], RX_DV, RX_ER hold time to RX_CLK
RX_CLK clock rise (20%-80%)
RX_CLK clock fall time (80%-20%)
Notes:
1. The symbols used for timing specifications herein follow the pattern of t
2. Guaranteed by design.
for inputs and t
timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the t
going to the high (H) state or setup time. Also, t
signals (D) went invalid (X) relative to the t
the clock reference symbol representation is based on three letters representing the clock of a particular functional. For
example, the subscript of t
with the appropriate letter: R (rise) or F (fall).
provides the MII receive AC timing specifications.
provides the AC test load for eTSEC.
shows the MII transmit AC timing diagram.
Parameter/Condition
MII Receive AC Timing Specifications
(first two letters of functional block)(reference)(state)(signal)(state)
TXD[3:0]
TX_CLK
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
TX_EN
TX_ER
Output
MRX
represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is used
Table 30. MII Receive AC Timing Specifications
Figure 12. MII Transmit AC Timing Diagram
t
MTXH
DD
/TV
MRX
Figure 13. eTSEC AC Test Load
DD
t
MTX
clock reference (K) going to the low (L) state or hold time. Note that, in general,
Z
of 2.5/ 3.3 V ± 5%.
MRDXKL
0
= 50 Ω
t
Symbol
MRXH
t
t
MRDXKH
MRDVKH
t
t
MRXR
t
MRXF
MRX
t
MRX
symbolizes MII receive timing (GR) with respect to the time data input
/t
MRX
2
2
2
1
t
MTKHDX
t
MTXF
for outputs. For example, t
(first two letters of functional block)(signal)(state) (reference)(state)
10.0
10.0
Min
1.0
1.0
35
—
—
R
Ethernet: Enhanced Three-Speed Ethernet (eTSEC)
t
L
MTXR
= 50 Ω
Typ
400
40
—
—
—
—
—
LV
DD
MRDVKH
/2
MRX
Max
symbolizes MII receive
4.0
4.0
65
—
—
—
—
clock reference (K)
Unit
ns
ns
ns
ns
ns
ns
%
35