MPC8572DS Freescale Semiconductor, MPC8572DS Datasheet - Page 131

• Manufacturer Part Number: MPC8572DS
• Description: KIT MPU POWERQUICC III
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8572DS

• Contents: Board
• Data Rate: 10 Mbps to 100 Mbps
• Memory Type: Flash, DDR, DDR2, DDR3, SDRAM
• Interface Type: I2C, Ethernet
• Operating Voltage: 3.3 V
• Data Bus Width: 32 bit
• Product: Development Tools
• Silicon Manufacturer: Freescale
• Core Architecture: Power Architecture
• Core Sub-architecture: PowerQUICC
• Silicon Core Number: MPC85xx
• Silicon Family Name: PowerQUICC III
• Rohs Compliant: Yes
• For Use With/related Products: MPC8572E
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Freescale Semiconductor
2. Populate this with a 10 Ω resistor for short-circuit/current-limiting protection.
3. The KEY location (pin 14) is not physically present on the COP header.
4. Although pin 12 is defined as a No-Connect, some debug tools may use pin 12 as an additional GND pin for improved
6. Asserting SRESET causes a machine check interrupt to the e500 cores.
1. The COP port and target board should be able to independently assert HRESET and TRST to the processor
5.This switch is included as a precaution for BSDL testing. The switch should be closed to position A during BSDL testing
Notes:
signal integrity.
to avoid accidentally asserting the TRST line. If BSDL testing is not being performed, this switch should be closed
to position B.
COP Connector
Physical Pinout
to fully control the processor as shown here.
13
15
11
1
1
3
5
7
9
Board Sources
No pin
From Target
KEY
10
12
16
4
6
8
2
(if any)
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
14
13
11
10
12
16
SRESET
HRESET
15
4
8
9
1
3
7
2
6
5
3
COP_CHKSTP_OUT
COP_VDD_SENSE
COP_CHKSTP_IN
COP_TMS
COP_TDO
COP_TDI
COP_TCK
COP_SRESET
COP_TRST
COP_HRESET
NC
Figure 66. JTAG Interface Connection
NC
NC
4
B
2
5
A
10 Ω
10 kΩ
10 kΩ
10 kΩ
10 kΩ
10 kΩ
10 kΩ
10 kΩ
10 kΩ
10 kΩ
OV
DD
SRESET
CKSTP_IN1
HRESET
TRST
CKSTP_OUT0
CKSTP_IN0
TMS
TDO
TDI
TCK
CKSTP_OUT1
System Design Information
1
1
6
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