MPC8572DS Freescale Semiconductor, MPC8572DS Datasheet - Page 75

• Manufacturer Part Number: MPC8572DS
• Description: KIT MPU POWERQUICC III
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8572DS

• Contents: Board
• Data Rate: 10 Mbps to 100 Mbps
• Memory Type: Flash, DDR, DDR2, DDR3, SDRAM
• Interface Type: I2C, Ethernet
• Operating Voltage: 3.3 V
• Data Bus Width: 32 bit
• Product: Development Tools
• Silicon Manufacturer: Freescale
• Core Architecture: Power Architecture
• Core Sub-architecture: PowerQUICC
• Silicon Core Number: MPC85xx
• Silicon Family Name: PowerQUICC III
• Rohs Compliant: Yes
• For Use With/related Products: MPC8572E
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Freescale Semiconductor
•
SD n _REF_CLK
SD n _REF_CLK
— For external DC-coupled connection, as described in
— For external AC-coupled connection, there is no common mode voltage requirement for the
Single-ended Mode
— The reference clock can also be single-ended. The SDn_REF_CLK input amplitude
— The SDn_REF_CLK input average voltage must be between 200 and 400 mV.
— To meet the input amplitude requirement, the reference clock inputs might need to be DC or
Figure 45. Differential Reference Clock Input DC Requirements (External DC-Coupled)
of the differential pair must have a single-ended swing less than 800mV and greater than
200mV. This requirement is the same for both external DC-coupled or AC-coupled connection.
Clock Receiver
requirement for average voltage (common mode voltage) to be between 100 mV and 400 mV.
Figure 45
scheme.
clock driver. Because the external AC-coupling capacitor blocks the DC level, the clock driver
and the SerDes reference clock receiver operate in different command mode voltages. The
SerDes reference clock receiver in this connection scheme has its common mode voltage set to
SGND_SRDSn. Each signal wire of the differential inputs is allowed to swing below and above
the command mode voltage (SGND_SRDSn).
input requirement for AC-coupled connection scheme.
(single-ended swing) must be between 400 mV and 800 mV peak-peak (from Vmin to Vmax)
with SDn_REF_CLK either left unconnected or tied to ground.
the SerDes reference clock input requirement for single-ended signaling mode.
AC-coupled externally. For the best noise performance, the reference of the clock could be DC
or AC-coupled into the unused phase (SDn_REF_CLK) through the same source impedance as
the clock input (SDn_REF_CLK) in use.
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
shows the SerDes reference clock input requirement for DC-coupled connection
200mV < Input Amplitude or Differential Peak < 800 mV
Characteristics,” the maximum average current requirements sets the
Figure 46
Section 15.2.1, “SerDes Reference
shows the SerDes reference clock
High-Speed Serial Interfaces (HSSI)
100 mV
<
Vcm
Vmax
Figure 47
Vmin
<
<
>
400 mV
800 mV
0 V
shows
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