MPC8572DS Freescale Semiconductor, MPC8572DS Datasheet - Page 85

• Manufacturer Part Number: MPC8572DS
• Description: KIT MPU POWERQUICC III
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8572DS

• Contents: Board
• Data Rate: 10 Mbps to 100 Mbps
• Memory Type: Flash, DDR, DDR2, DDR3, SDRAM
• Interface Type: I2C, Ethernet
• Operating Voltage: 3.3 V
• Data Bus Width: 32 bit
• Product: Development Tools
• Silicon Manufacturer: Freescale
• Core Architecture: Power Architecture
• Core Sub-architecture: PowerQUICC
• Silicon Core Number: MPC85xx
• Silicon Family Name: PowerQUICC III
• Rohs Compliant: Yes
• For Use With/related Products: MPC8572E
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16.4.2
The TX eye diagram in
Figure
There are two eye diagrams that must be met for the transmitter. Both eye diagrams must be aligned in
time using the jitter median to locate the center of the eye diagram. The different eye diagrams differ in
voltage depending whether it is a transition bit or a de-emphasized bit. The exact reduced voltage level of
the de-emphasized bit is always relative to the transition bit.
The eye diagram must be valid for any 250 consecutive UIs.
A recovered TX UI is calculated over 3500 consecutive unit intervals of sample data. The eye diagram is
created using all edges of the 250 consecutive UI in the center of the 3500 UI used for calculating the TX
UI.
Freescale Semiconductor
57) in place of any real PCI Express interconnect + RX component.
Figure 55. Minimum Transmitter Timing and Voltage Output Compliance Specifications
Transmitter Compliance Eye Diagrams
It is recommended that the recovered TX UI is calculated using all edges in
the 3500 consecutive UI interval with a fit algorithm using a minimization
merit function (that is, least squares and median deviation fits).
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
(D+ D– Crossing Point)
V
RX-DIFF
Figure 55
= 0 mV
566 mV (3 dB ) >= V
is specified using the passive compliance/test measurement load (see
0.07 UI = UI – 0.3 UI (J
V
V
TX-DIFFp-p-MIN
TX-DIFFp-p-MIN
[De-Emphasized Bit]
[Transition Bit]
[Transition Bit]
TX-DIFFp-p-MIN
NOTE
= 800 mV
= 800 mV
TX-TOTAL-MAX
>= 505 mV (4 dB )
(D+ D– Crossing Point)
)
V
TX-DIFF
= 0 mV
PCI Express
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