MPC8572DS Freescale Semiconductor, MPC8572DS Datasheet - Page 18

• Manufacturer Part Number: MPC8572DS
• Description: KIT MPU POWERQUICC III
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8572DS

• Contents: Board
• Data Rate: 10 Mbps to 100 Mbps
• Memory Type: Flash, DDR, DDR2, DDR3, SDRAM
• Interface Type: I2C, Ethernet
• Operating Voltage: 3.3 V
• Data Bus Width: 32 bit
• Product: Development Tools
• Silicon Manufacturer: Freescale
• Core Architecture: Power Architecture
• Core Sub-architecture: PowerQUICC
• Silicon Core Number: MPC85xx
• Silicon Family Name: PowerQUICC III
• Rohs Compliant: Yes
• For Use With/related Products: MPC8572E
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Required assertion time of HRESET
Minimum assertion time for SRESET
PLL config input setup time with stable SYSCLK before HRESET
negation
Input setup time for POR configs (other than PLL config) with respect to
negation of HRESET
Input hold time for all POR configs (including PLL config) with respect to
negation of HRESET
Maximum valid-to-high impedance time for actively driven POR configs
with respect to negation of HRESET
Notes:
1. SYSCLK is the primary clock input for the MPC8572E.
2. Reset assertion timing requirements for DDR3 DRAMs may differ.
RESET Initialization
4.5
Note the following eTSEC FIFO mode maximum speed restrictions based on platform (CCB) frequency.
For FIFO GMII modes (both 8 and 16 bit) and 16-bit encoded FIFO mode:
For 8-bit encoded FIFO mode:
4.6
For information on the input clocks of other functional blocks of the platform, such as SerDes and eTSEC,
see the respective sections of this document.
5
Table 9
18
FIFO TX/RX clock frequency <= platform clock (CCB) frequency/4.2
For example, if the platform (CCB) frequency is 533 MHz, the FIFO TX/RX clock frequency
should be no more than 127 MHz.
FIFO TX/RX clock frequency <= platform clock (CCB) frequency/3.2
For example, if the platform (CCB) frequency is 533 MHz, the FIFO TX/RX clock frequency
should be no more than 167 MHz.
RESET Initialization
describes the AC electrical specifications for the RESET initialization timing.
Platform to eTSEC FIFO Restrictions
Other Input Clocks
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Parameter/Condition
Table 9. RESET Initialization Timing Specifications
Min
100
100
—
3
4
2
Max
—
—
—
—
—
5
Freescale Semiconductor
SYSCLKs
SYSCLKs
SYSCLKs
SYSCLKs
Unit
μs
μs
Notes
—
2
1
1
1
1