MPC8572DS Freescale Semiconductor, MPC8572DS Datasheet - Page 77

KIT MPU POWERQUICC III

MPC8572DS

Manufacturer Part Number
MPC8572DS
Description
KIT MPU POWERQUICC III
Manufacturer
Freescale Semiconductor
Series
PowerQUICC III™r
Type
MPUr
Datasheets

Specifications of MPC8572DS

Contents
Board
Data Rate
10 Mbps to 100 Mbps
Memory Type
Flash, DDR, DDR2, DDR3, SDRAM
Interface Type
I2C, Ethernet
Operating Voltage
3.3 V
Data Bus Width
32 bit
Product
Development Tools
Silicon Manufacturer
Freescale
Core Architecture
Power Architecture
Core Sub-architecture
PowerQUICC
Silicon Core Number
MPC85xx
Silicon Family Name
PowerQUICC III
Rohs Compliant
Yes
For Use With/related Products
MPC8572E
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Figure 48
assumes that the DC levels of the clock driver chip is compatible with MPC8572E SerDes reference clock
input’s DC requirement.
Freescale Semiconductor
HCSL CLK Driver Chip
Total 50 Ω. Assume clock driver’s
output impedance is about 16 Ω.
Clock Driver
Clock Driver
Figure 48. DC-Coupled Differential Connection with HCSL Clock Driver (Reference Only)
shows the SerDes reference clock connection reference circuits for HCSL type clock driver. It
CLK_Out
CLK_Out
CLK_Out
Figure 48
fact that clock driver chip's internal structure, output impedance and
termination requirements are different between various clock driver chip
manufacturers, it is very possible that the clock circuit reference designs
provided by clock driver chip vendor are different from what is shown
below. They might also vary from one vendor to the other. Therefore,
Freescale Semiconductor can neither provide the optimal clock driver
reference circuits, nor guarantee the correctness of the following clock
driver connection reference circuits. The system designer is recommended
to contact the selected clock driver chip vendor for the optimal reference
circuits with the MPC8572E SerDes reference clock receiver requirement
provided in this document.
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
to
33 Ω
33 Ω
Figure 51
Clock driver vendor dependent
source termination resistor
100 Ω differential PWB trace
below are for conceptual reference only. Due to the
NOTE
SD n _REF_CLK
SD n _REF_CLK
50 Ω
High-Speed Serial Interfaces (HSSI)
50 Ω
MPC8572E
SerDes Refer.
CLK Receiver
77

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