MPC8572DS Freescale Semiconductor, MPC8572DS Datasheet - Page 97

• Manufacturer Part Number: MPC8572DS
• Description: KIT MPU POWERQUICC III
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8572DS

• Contents: Board
• Data Rate: 10 Mbps to 100 Mbps
• Memory Type: Flash, DDR, DDR2, DDR3, SDRAM
• Interface Type: I2C, Ethernet
• Operating Voltage: 3.3 V
• Data Bus Width: 32 bit
• Product: Development Tools
• Silicon Manufacturer: Freescale
• Core Architecture: Power Architecture
• Core Sub-architecture: PowerQUICC
• Silicon Core Number: MPC85xx
• Silicon Family Name: PowerQUICC III
• Rohs Compliant: Yes
• For Use With/related Products: MPC8572E
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

17.7
For each baud rate at which an LP-Serial receiver is specified to operate, the receiver shall meet the
corresponding Bit Error Rate specification
receiver test signal (exclusive of sinusoidal jitter) falls entirely within the unshaded portion of the Receiver
Input Compliance Mask shown in
the receiver test signal is measured at the input pins of the receiving device with the device replaced with
a 100-Ω +/– 5% differential resistive load.
17.8
Because the LP-Serial electrical specification are guided by the XAUI electrical interface specified in
Clause 47 of IEEE 802.3ae-2002, the measurement and test requirements defined here are similarly guided
by Clause 47. Additionally, the CJPAT test pattern defined in Annex 48A of IEEE 802.3ae-2002 is
Freescale Semiconductor
-V
-V
Receiver Eye Diagrams
Measurement and Test Requirements
V
V
DIFF
DIFF
Table 75. Receiver Input Compliance Mask Parameters Exclusive of Sinusoidal Jitter
DIFF
DIFF
1.25 GBaud
2.5 GBaud
3.125 GBaud
min
max
max
min
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
0
0
Receiver Type
Figure 60. Receiver Input Compliance Mask
Figure 60
A
(Table
V
DIFF
with the parameters specified in
min (mV) V
100
100
100
72,
B
Table
Time (UI)
DIFF
73, and
max (mV)
800
800
800
1-B
Table
A (UI)
74) when the eye pattern of the
0.275
0.275
0.275
1-A
Table
75. The eye pattern of
B (UI)
0.400
0.400
0.400
Serial RapidIO
1
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