MPC8572DS Freescale Semiconductor, MPC8572DS Datasheet - Page 24

• Manufacturer Part Number: MPC8572DS
• Description: KIT MPU POWERQUICC III
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8572DS

• Contents: Board
• Data Rate: 10 Mbps to 100 Mbps
• Memory Type: Flash, DDR, DDR2, DDR3, SDRAM
• Interface Type: I2C, Ethernet
• Operating Voltage: 3.3 V
• Data Bus Width: 32 bit
• Product: Development Tools
• Silicon Manufacturer: Freescale
• Core Architecture: Power Architecture
• Core Sub-architecture: PowerQUICC
• Silicon Core Number: MPC85xx
• Silicon Family Name: PowerQUICC III
• Rohs Compliant: Yes
• For Use With/related Products: MPC8572E
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DDR2 and DDR3 SDRAM Controller
24
At recommended operating conditions with GV
<= 667 MHz
Note:
1. The symbols used for timing specifications follow the pattern of t
2. All MCK/MCK referenced measurements are made from the crossing of the two signals ±0.1 V.
3. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ/MECC/MDM/MDQS.
4. Note that t
5. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ),
6. All outputs are referenced to the rising edge of MCK[n] at the pins of the microprocessor. Note that t
(reference)(state)
be read as DDR timing (DD) from the rising or falling edge of the reference clock (KH or KL) until the output went
invalid (AX or DX). For example, t
(K) goes from the high (H) state until outputs (A) are setup (S) or output valid time. Also, t
timing (DD) for the time t
output hold time.
timing (DD) from the rising edge of the MCK[n] clock (KH) until the MDQS signal is valid (MH). t
modified through control of the MDQS override bits (called WR_DATA_DELAY) in the TIMING_CFG_2 register. This
typically be set to the same delay as in DDR_SDRAM_CLK_CNTL[CLK_ADJUST]. The timing parameters listed in
the table assume that these 2 parameters have been set to the same adjustment value. See the MPC8572E
PowerQUICC™ III Integrated Host Processor Family Reference Manual for a description and understanding of the
timing modifications enabled by use of these bits.
ECC (MECC), or data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the
microprocessor.
the symbol conventions described in note 1.
Table 18. DDR2 and DDR3 SDRAM Interface Output AC Timing Specifications (continued)
For the ADDR/CMD setup and hold specifications in
assumed that the clock control register is set to adjust the memory clocks by
1/2 applied cycle.
DDKHMH
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
for inputs and t
Parameter
follows the symbol conventions described in note 1. For example, t
MCK
(first two letters of functional block)(reference)(state)(signal)(state)
memory clock reference (K) goes low (L) until data outputs (D) are invalid (X) or data
DDKHAS
DD
of 1.8 V ± 5% for DDR2 or 1.5 V ± 5% for DDR3.
symbolizes DDR timing (DD) for the time t
Symbol
t
DDKHME
NOTE
1
(first two letters of functional block)(signal)(state)
–0.6
Min
Table
for outputs. Output hold time can
18, it is
MCK
Max
0.6
DDKHMH
memory clock reference
DDKLDX
Freescale Semiconductor
describes the DDR
DDKHMH
symbolizes DDR
DDKHMP
Unit
ns
can be
follows
Notes
6