MPC8572DS Freescale Semiconductor, MPC8572DS Datasheet - Page 32

• Manufacturer Part Number: MPC8572DS
• Description: KIT MPU POWERQUICC III
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8572DS

• Contents: Board
• Data Rate: 10 Mbps to 100 Mbps
• Memory Type: Flash, DDR, DDR2, DDR3, SDRAM
• Interface Type: I2C, Ethernet
• Operating Voltage: 3.3 V
• Data Bus Width: 32 bit
• Product: Development Tools
• Silicon Manufacturer: Freescale
• Core Architecture: Power Architecture
• Core Sub-architecture: PowerQUICC
• Silicon Core Number: MPC85xx
• Silicon Family Name: PowerQUICC III
• Rohs Compliant: Yes
• For Use With/related Products: MPC8572E
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Ethernet: Enhanced Three-Speed Ethernet (eTSEC)
8.2.2
This section describes the GMII transmit and receive AC timing specifications.
8.2.2.1
Table 27
32
At recommended operating conditions with LV
GMII data TXD[7:0], TX_ER, TX_EN setup time
GTX_CLK to GMII data TXD[7:0], TX_ER, TX_EN delay
GTX_CLK data clock rise time (20%-80%)
GTX_CLK data clock fall time (80%-20%)
Notes:
1. The symbols used for timing specifications herein follow the pattern t
2. Guaranteed by design.
for inputs and t
transmit timing (GT) with respect to the t
signals (D) reaching the valid state (V) to state or setup time. Also, t
to the t
time. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a
particular functional. For example, the subscript of t
the latter convention is used with the appropriate letter: R (rise) or F (fall).
GTX
provides the GMII transmit AC timing specifications.
RX_CLK
RXD[7:0]
RX_DV
RX_ER
GMII AC Timing Specifications
clock reference (K) going to the high state (H) relative to the time date input signals (D) going invalid (X) or hold
GMII Transmit AC Timing Specifications
(first two letters of functional block)(reference)(state)(signal)(state)
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Parameter/Condition
t
FIRH
Table 27. GMII Transmit AC Timing Specifications
Figure 8. FIFO Receive AC Timing Diagram
DD
/TV
t
GTX
FIR
DD
clock reference (K) going to the high state (H) relative to the time date input
of 2.5/ 3.3 V ± 5%.
t
FIRDV
GTX
valid data
represents the GMII(G) transmit (TX) clock. For rise and fall times,
t
FIRDX
Symbol
GTKHDX
t
t
GTKHDV
t
t
GTKHDX
GTXR
GTXF
for outputs. For example, t
(first two letters of functional block)(signal)(state) (reference)(state)
2
2
symbolizes GMII transmit timing (GT) with respect
1
t
FIRF
Min
2.5
0.5
—
—
t
FIRR
Typ
—
—
—
—
GTKHDV
Freescale Semiconductor
symbolizes GMII
Max
5.0
1.0
1.0
—
Unit
ns
ns
ns
ns