MPC8572DS Freescale Semiconductor, MPC8572DS Datasheet - Page 42

• Manufacturer Part Number: MPC8572DS
• Description: KIT MPU POWERQUICC III
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8572DS

• Contents: Board
• Data Rate: 10 Mbps to 100 Mbps
• Memory Type: Flash, DDR, DDR2, DDR3, SDRAM
• Interface Type: I2C, Ethernet
• Operating Voltage: 3.3 V
• Data Bus Width: 32 bit
• Product: Development Tools
• Silicon Manufacturer: Freescale
• Core Architecture: Power Architecture
• Core Sub-architecture: PowerQUICC
• Silicon Core Number: MPC85xx
• Silicon Family Name: PowerQUICC III
• Rohs Compliant: Yes
• For Use With/related Products: MPC8572E
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

At recommended operating conditions with LV
Ethernet: Enhanced Three-Speed Ethernet (eTSEC)
Figure 20
Figure 21
8.3
Each SGMII port features a 4-wire AC-Coupled serial link from the dedicated SerDes 2 interface of
MPC8572E as shown in
output pin of the SerDes transmitter differential pair features 50-Ω output impedance. Each input of the
SerDes receiver differential pair features 50-Ω on-die termination to SGND_SRDS2 (xcorevss). The
reference circuit of the SerDes transmitter and receiver is shown in
When an eTSEC port is configured to operate in SGMII mode, the parallel interface’s output signals of
this eTSEC port can be left floating. The input signals should be terminated based on the guidelines
described in
the desired POR configuration requirement on these pins, if applicable.
42
RXD[1:0], CRS_DV, RX_ER hold time to
TSECn_TX_CLK rising edge
Note:
1. The symbols used for timing specifications herein follow the pattern of t
for inputs and t
timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the t
going to the high (H) state or setup time. Also, t
signals (D) went invalid (X) relative to the t
the clock reference symbol representation is based on three letters representing the clock of a particular functional. For
example, the subscript of t
with the appropriate letter: R (rise) or F (fall).
SGMII Interface Electrical Characteristics
provides the AC test load for eTSEC.
shows the RMII receive AC timing diagram.
Section 21.5, “Connection Recommendations,”
TSEC n _TX_CLK
Parameter/Condition
(first two letters of functional block)(reference)(state)(signal)(state)
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
RXD[1:0]
CRS_DV
RX_ER
Table 36. RMII Receive AC Timing Specifications (continued)
Output
MRX
Figure
represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is used
Figure 21. RMII Receive AC Timing Diagram
22, where C
DD
/TV
t
RMRH
MRX
Figure 20. eTSEC AC Test Load
t
RMRDV
DD
Z
clock reference (K) going to the low (L) state or hold time. Note that, in general,
of 2.5/ 3.3 V ± 5%.
MRDXKL
0
t
RMR
= 50 Ω
TX
is the external (on board) AC-Coupled capacitor. Each
symbolizes MII receive timing (GR) with respect to the time data input
Symbol
t
RMRDX
Valid Data
1
t
RMRF
for outputs. For example, t
(first two letters of functional block)(signal)(state) (reference)(state)
as long as such termination does not violate
R
Min
2.0
L
= 50 Ω
t
Figure
RMRDX
t
RMRR
54.
Typ
LV
—
DD
MRDVKH
/2
MRX
Freescale Semiconductor
symbolizes MII receive
Max
clock reference (K)
—
Unit
ns