MC68HC11E1CFN3 Freescale Semiconductor, MC68HC11E1CFN3 Datasheet - Page 68

IC MCU 3MHZ 512 EEPROM 52-PLCC

MC68HC11E1CFN3

Manufacturer Part Number
MC68HC11E1CFN3
Description
IC MCU 3MHZ 512 EEPROM 52-PLCC
Manufacturer
Freescale Semiconductor
Series
HC11r
Datasheet

Specifications of MC68HC11E1CFN3

Core Processor
HC11
Core Size
8-Bit
Speed
3MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
38
Program Memory Type
ROMless
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SCI, SPI
Maximum Clock Frequency
3 MHz
Number Of Programmable I/os
22
Number Of Timers
16 bit
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Program Memory Size
-
Lead Free Status / Rohs Status
 Details

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Analog-to-Digital (A/D) Converter
3.6 Single-Channel Operation
3.7 Multiple-Channel Operation
Data Sheet
68
The two types of single-channel operation are:
The two types of multiple-channel operation are:
1. When SCAN = 0, the single selected channel is converted four consecutive
2. When SCAN = 1, conversions continue to be performed on the selected
1. When SCAN = 0, a selected group of four channels is converted one time
2. When SCAN = 1, conversions continue to be performed on the selected
times. The first result is stored in A/D result register 1 (ADR1), and the fourth
result is stored in ADR4. After the fourth conversion is complete, all
conversion activity is halted until a new conversion command is written to
the ADCTL register.
channel with the fifth conversion being stored in register ADR1 (overwriting
the first conversion result), the sixth conversion overwriting ADR2, and so
on.
each. The first result is stored in A/D result register 1 (ADR1), and the fourth
result is stored in ADR4. After the fourth conversion is complete, all
conversion activity is halted until a new conversion command is written to
the ADCTL register.
group of channels with the fifth conversion being stored in register ADR1
(replacing the earlier conversion result for the first channel in the group), the
sixth conversion overwriting ADR2, and so on.
Freescale Semiconductor, Inc.
For More Information On This Product,
1. Used for factory testing
Analog-to-Digital (A/D) Converter
Go to: www.freescale.com
Table 3-1. Converter Channel Assignments
Channel
Number
9 – 12
13
14
15
16
1
2
3
4
5
6
7
8
Reserved
Reserved
(V
Channel
Signal
V
V
RH
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
RH
RL
)/2
(1)
(1)
(1)
(1)
Result in ADRx
if MULT = 1
ADR1
ADR2
ADR3
ADR4
ADR1
ADR2
ADR3
ADR4
ADR1
ADR2
ADR3
ADR4
M68HC11E Family — Rev. 5
MOTOROLA

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