R5F212D8SNFP#U0 Renesas Electronics America, R5F212D8SNFP#U0 Datasheet - Page 117

• Manufacturer Part Number: R5F212D8SNFP#U0
• Description: IC R8C/2D MCU FLASH 64KB 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/2Dr

Specifications of R5F212D8SNFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• For Use With: R0K5212D8S001BE - KIT STARTER FOR R8C/2DR0K5212D8S000BE - KIT DEV FOR R8C/2D
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/2C Group, R8C/2D Group
Rev.2.00
REJ09B0339-0200
9.
The bus cycles differ when accessing ROM/RAM, and when accessing SFR.
Table 9.1 lists Bus Cycles by Access Space of the R8C/2C Group and Table 9.2 lists Bus Cycles by Access Space of
the R8C/2D Group.
ROM/RAM and SFR are connected to the CPU by an 8-bit bus. When accessing in word (16-bit) units, these areas are
accessed twice in 8-bit units.
Table 9.3 lists Access Units and Bus Operations and Table 9.4 lists Access Units and Bus Operations of SFR (address
0200h to 02FFh).
Table 9.1
Table 9.2
Table 9.3
SFR (address 0000h to 01FFh)
SFR (address 0200h to 02FFh)
ROM/RAM
SFR (address 0000h to 01FFh)/Data flash 2 cycles of CPU clock
SFR (address 0200h to 02FFh)
Program ROM/RAM
Bus
Even address
Even address
Odd address
Word access
Odd address
Word access
Byte access
Byte access
Area
Dec 05, 2007
Bus Cycles by Access Space of the R8C/2C Group
Bus Cycles by Access Space of the R8C/2D Group
Access Units and Bus Operations
Access Area
Access Area
CPU clock
Address
Data
CPU
Address
Data
CPU
Address
Data
CPU
Address
Data
clock
clock
clock
SFR (address 0000h to 01FFh), data flash
Page 94 of 585
Even
Odd
Data
Data
Even
Odd
2 cycles of CPU clock
3 cycles of CPU clock
1 cycle of CPU clock
3 cycles of CPU clock
1 cycle of CPU clock
Even + 1
Odd + 1
Data
Data
Data
Data
Bus Cycle
Bus Cycle
CPU
Address
Data
CPU
Address
Data
CPU
Address
Data
CPU
Address
Data
clock
clock
clock
clock
ROM (program ROM), RAM
Even
Even
Odd
Odd
Data
Data
Data
Data
Even + 1
Odd + 1
Data
Data
9. Bus