R5F212D8SNFP#U0 Renesas Electronics America, R5F212D8SNFP#U0 Datasheet - Page 403

• Manufacturer Part Number: R5F212D8SNFP#U0
• Description: IC R8C/2D MCU FLASH 64KB 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/2Dr

Specifications of R5F212D8SNFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• For Use With: R0K5212D8S001BE - KIT STARTER FOR R8C/2DR0K5212D8S000BE - KIT DEV FOR R8C/2D
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/2C Group, R8C/2D Group
Rev.2.00
REJ09B0339-0200
Figure 15.4
UARTi Transmit/Receive Mode Register (i = 0 to 2)
UARTi Bit Rate Register (i = 0 to 2)
b7 b6 b5 b4
0
b7
NOTES:
1.
2.
3.
Write to this register w hile the serial I/O is neither transmitting nor receiving.
Use the MOV instruction to w rite to this register.
After setting the CLK0 to CLK1 bits of the UiC0 register, w rite to the UiBRG register.
Dec 05, 2007
b3 b2 b1
Registers U0MR to U2MR and U0BRG to U2BRG
b0
b0
Assuming the set value is n, UiBRG divides the count source by n+1
Bit Symbol
Symbol
Symbol
U0BRG
U1BRG
U2BRG
CKDIR
U0MR
U1MR
U2MR
SMD0
SMD1
SMD2
PRYE
STPS
PRY
(b7)
Page 380 of 585
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Serial I/O mode select bits
Internal/external clock select bit 0 : Internal clock
Stop bit length select bit
Odd/even parity select bit
Parity enable bit
Reserved bit
(1, 2, 3)
Address
Bit Name
00A0h
00A8h
0160h
Function
Address
00A1h
00A9h
0161h
b2 b1 b0
0 0 0 : Serial interface disabled
0 0 1 : Clock synchronous serial I/O mode
1 0 0 : UART mode transfer data 7 bits long
1 0 1 : UART mode transfer data 8 bits long
1 1 0 : UART mode transfer data 9 bits long
Other than above : Do not set.
1 : External clock
0 : 1 stop bit
1 : 2 stop bits
Enable w hen PRYE = 1
0 : Odd parity
1 : Even parity
0 : Parity disabled
1 : Parity enabled
Set to 0.
After Reset
Function
00h
00h
00h
Setting Range
After Reset
00h to FFh
Undefined
Undefined
Undefined
15. Serial Interface
RW
RW
RW
RW
RW
RW
RW
RW
RW
WO
RW