R5F212D8SNFP#U0 Renesas Electronics America, R5F212D8SNFP#U0 Datasheet - Page 141

• Manufacturer Part Number: R5F212D8SNFP#U0
• Description: IC R8C/2D MCU FLASH 64KB 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/2Dr

Specifications of R5F212D8SNFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• For Use With: R0K5212D8S001BE - KIT STARTER FOR R8C/2DR0K5212D8S000BE - KIT DEV FOR R8C/2D
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/2C Group, R8C/2D Group
Rev.2.00
REJ09B0339-0200
Figure 10.15
(flash memory stops)
10.5.3.3
mode
Stop
Interrupt
request
generated
FMR0 Register
(flash memory
The MCU exits stop mode by a reset or peripheral function interrupt.
Figure 10.15 shows the Time from Stop Mode to Interrupt Routine Execution.
When using a peripheral function interrupt to exit stop mode, set up the following before setting the CM10 bit
to 1.
If the clock used immediately before stop mode is a system clock and stop mode is exited by a peripheral
function interrupt, the CPU clock becomes the previous system clock divided by 8.
FMSTP Bit
operates)
(1) Set the interrupt priority level in bits ILVL2 to ILVL0 of the peripheral function interrupts to be used for
(2) Set the I flag to 1.
(3) Operates the peripheral function to be used for exiting stop mode.
Dec 05, 2007
stability time
0
1
Internal
power
150 µs
(max.)
exiting stop mode. Set bits ILVL2 to ILVL0 of the peripheral function interrupts that are not to be used
for exiting stop mode to 000b (interrupt disabled).
When exiting by a peripheral function interrupt, the interrupt sequence is executed when an interrupt
request is generated and the CPU clock supply is started.
T0
Exiting Stop Mode
Time from Stop Mode to Interrupt Routine Execution
0 (system clock)
0 (system clock)
Oscillation time of
CPU clock source
used immediately
before stop mode
1 (XCIN clock)
1 (XCIN clock)
CM0 Register
CM07 Bit
Page 118 of 585
T1
× 12 cycles + 30 µs (max.)
× 12 cycles + 30 µs (max.)
Time until Flash Memory
Period of system clock
Period of system clock
Period of XCIN clock
Period of XCIN clock
activation sequence
is Activated (T2)
Flash memory
× 12 cycles
× 12 cycles
T2
Time until CPU Clock
Period of CPU clock
CPU clock restart
is Supplied (T3)
Same as above
Same as above
Same as above
× 6 cycles
sequence
T3
Period of CPU clock
Interrupt sequence
Time for Interrupt
Same as above
Same as above
Same as above
Sequence (T4)
× 20 cycles
10. Clock Generation Circuit
T4
Following total
time of T0 to
T4 is the time
from stop
mode until an
interrupt
handling is
executed.
Remarks