R5F212D8SNFP#U0 Renesas Electronics America, R5F212D8SNFP#U0 Datasheet - Page 325

• Manufacturer Part Number: R5F212D8SNFP#U0
• Description: IC R8C/2D MCU FLASH 64KB 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/2Dr

Specifications of R5F212D8SNFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• For Use With: R0K5212D8S001BE - KIT STARTER FOR R8C/2DR0K5212D8S000BE - KIT DEV FOR R8C/2D
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/2C Group, R8C/2D Group
Rev.2.00
REJ09B0339-0200
Figure 14.117 TRDFCR Register in Reset Synchronous PWM Mode
Timer RD Function Control Register
b7 b6 b5 b4
NOTES:
1.
2.
3.
When bits CMD1 to CMD0 are set to 01b, 10b, or 11b, the MCU enters reset synchronous PWM mode or
complementary PWM mode in spite of the setting of the TRDPMR register.
Set bits CMD1 to CMD0 w hen both the TSTART0 and TSTART1 bits are set to 0 (count stops).
When bits CMD1 to CMD0 are set to 00b (timer mode, PWM mode, or PWM3 mode), the setting of the PWM3 bit is
enabled.
Dec 05, 2007
b3 b2
b1 b0
0 1
Bit Symbol
TRDFCR
ADTRG
Symbol
STCLK
ADEG
PWM3
CMD0
CMD1
OLS0
OLS1
Page 302 of 585
Combination mode select bits
Normal-phase output level select bit
(in reset synchronous PWM mode or
complementary PWM mode)
Counter-phase output level select bit
(in reset synchronous PWM mode or
complementary PWM mode)
A/D trigger enable bit
(in complementary PWM mode)
A/D trigger edge select bit
(in complementary PWM mode)
External clock input select bit
PWM3 mode select bit
Address
Bit Name
013Ah
(3)
(1, 2)
Set to 01b (reset synchronous PWM
mode) in reset synchronous PWM mode.
0 : Initial output “H”
1 : Initial output “L”
0 : Initial output “H”
1 : Initial output “L”
This bit is disabled in reset synchronous
PWM mode.
This bit is disabled in reset synchronous
PWM mode.
0 : External clock input disabled
1 : External clock input enabled
This bit is disabled in reset synchronous
PWM mode.
Active level “L”
Active level “H”
Active level “L”
Active level “H”
After Reset
10000000b
Function
14. Timers
RW
RW
RW
RW
RW
RW
RW
RW
RW