R5F212D8SNFP#U0 Renesas Electronics America, R5F212D8SNFP#U0 Datasheet - Page 598

• Manufacturer Part Number: R5F212D8SNFP#U0
• Description: IC R8C/2D MCU FLASH 64KB 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/2Dr

Specifications of R5F212D8SNFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• For Use With: R0K5212D8S001BE - KIT STARTER FOR R8C/2DR0K5212D8S000BE - KIT DEV FOR R8C/2D
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/2C Group, R8C/2D Group
Rev.2.00
REJ09B0339-0200
22.8
22.8.1
Table 22.2
NOTES:
Mode
EW0 During auto-erasure
22.8.1.1
22.8.1.2
22.8.1.3
1. Do not use the address match interrupt while a command is being executed because the vector of
2. Do not use a non-maskable interrupt while block 0 is being automatically erased because the fixed
Before entering CPU rewrite mode (EW0 mode), select 5 MHz or below for the CPU clock using the CM06 bit
in the CM0 register and bits CM16 to CM17 in the CM1 register. This does not apply to EW1 mode.
The following instructions cannot be used in EW0 mode because they reference data in the flash memory:
UND, INTO, and BRK.
Table 22.2 lists the EW0 Mode Interrupts and Table 22.3 lists the EW1 Mode Interrupts.
the address match interrupt is allocated in ROM.
vector is allocated in block 0.
Notes on Flash Memory
Auto-programming
Dec 05, 2007
CPU Rewrite Mode
Operating Speed
Prohibited Instructions
Interrupts
EW0 Mode Interrupts
Status
Page 575 of 585
Any interrupt can be used
by allocating a vector in
RAM
Interrupt Request is
When Maskable
Acknowledged
Once an interrupt request is acknowledged,
auto-programming or auto-erasure is
forcibly stopped immediately and the flash
memory is reset. Interrupt handling starts
after the fixed period and the flash memory
restarts. Since the block during auto-
erasure or the address during auto-
programming is forcibly stopped, the
normal value may not be read. Execute
auto-erasure again and ensure it completes
normally.
Since the watchdog timer does not stop
during the command operation, interrupt
requests may be generated. Reset the
watchdog timer regularly.
When Watchdog Timer, Oscillation Stop
Detection, Voltage Monitor 1, or Voltage
Monitor 2 Interrupt Request is
Acknowledged
22. Usage Notes