R5F212D8SNFP#U0 Renesas Electronics America, R5F212D8SNFP#U0 Datasheet - Page 288

• Manufacturer Part Number: R5F212D8SNFP#U0
• Description: IC R8C/2D MCU FLASH 64KB 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/2Dr

Specifications of R5F212D8SNFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• For Use With: R0K5212D8S001BE - KIT STARTER FOR R8C/2DR0K5212D8S000BE - KIT DEV FOR R8C/2D
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/2C Group, R8C/2D Group
Rev.2.00
REJ09B0339-0200
Figure 14.82
TRDIOji input signal
14.4.5.1
fOCO40M
Sampling clock
TRDIOji input signal
Input signal through
digital filtering
TRDCLK
The TRDIOji input is sampled, and when the sampled input level matches 3 times, its level is determined.
Select the digital filter function and sampling clock by the TRDDFi register.
f32
f8
f4
f2
f1
Dec 05, 2007
= 011b
Timer RD operation clock
= 100b
= 010b
i = 0 or 1, j = either A, B, C, or D
TCK0 to TCK2: Bits in TRDCRi register
DFCK0 to DFCK1 and DFj: Bits in TRDDF register
IOA0 to IOA2 and IOB0 to IOB2: Bits in TRDIORAi register
IOC0 to IOC3 and IOD0 to IOD3: Bits in TRDIORCi register
Digital Filter
Block Diagram of Digital Filter
Clock period selected by
= 001b
bits TCK2 to TCK0 or
bits DFCK1 to DFCK0
= 101b
D
D
f1, fOCO40M)
= 000b
Latch
Latch
TCK2 to TCK0
C
C
Q
Q
= 110b
Page 265 of 585
Count source
D
f32
f8
f1
Latch
C
= 01b
= 10b
= 00b
= 11b
DFCK1 to DFCK0
Q
Transmission cannot be
performed without 3-time match
because the input signal is
assumed to be noise.
D
Latch
C
Sampling clock
Q
D
Latch
C
Q
detection
Match
circuit
Signal transmission delayed
up to 5-sampling clock
signal change with
Recognition of the
3-time match
1
0
DFj
Edge detection
IOC3 to IOC0
IOD3 to IOD0
IOA2 to IOA0
IOB2 to IOB0
circuit
14. Timers