R5F212D8SNFP#U0 Renesas Electronics America, R5F212D8SNFP#U0 Datasheet - Page 285

• Manufacturer Part Number: R5F212D8SNFP#U0
• Description: IC R8C/2D MCU FLASH 64KB 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/2Dr

Specifications of R5F212D8SNFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• For Use With: R0K5212D8S001BE - KIT STARTER FOR R8C/2DR0K5212D8S000BE - KIT DEV FOR R8C/2D
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/2C Group, R8C/2D Group
Rev.2.00
REJ09B0339-0200
Figure 14.78
Figure 14.79
Timer RD Interrupt Enable Register i (i = 0 or 1)
Timer RD Counter i (i = 0 or 1)
(b15)
b7 b6 b5 b4 b3 b2
b7
NOTE:
1.
Access the TRDi register in 16-bit units. Do not access it in 8-bit units.
Dec 05, 2007
Registers TRDIER0 to TRDIER1 in Input Capture Function
Registers TRD0 to TRD1 in Input Capture Function
b1 b0
(b8)
b0
b7
Count the count source. Count operation is incremented.
When an overflow occurs, the OVF bit in the TRDSRi register is set to 1.
Bit Symbol
TRDIER0
TRDIER1
(b7-b5)
Symbol
IMIEA
IMIEB
IMIEC
IMIED
OVIE
Page 262 of 585
—
(1)
Input capture/compare match
interrupt enable bit A
Input capture/compare match
interrupt enable bit B
Input capture/compare match
interrupt enable bit C
Input capture/compare match
interrupt enable bit D
Overflow /underflow interrupt
enable bit
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
b0
Symbol
TRD0
TRD1
Address
Bit Name
0144h
0154h
Function
0 : Disable interrupt (IMIA) by the IMFA bit
1 : Enable interrupt (IMIA) by the IMFA bit
0 : Disable interrupt (IMIB) by the IMFB bit
1 : Enable interrupt (IMIB) by the IMFB bit
0 : Disable interrupt (IMIC) by the IMFC bit
1 : Enable interrupt (IMIC) by the IMFC bit
0 : Disable interrupt (IMID) by the IMFD bit
1 : Enable interrupt (IMID) by the IMFD bit
0 : Disable interrupt (OVI) by the OVF bit
1 : Enable interrupt (OVI) by the OVF bit
0147h-0146h
0157h-0156h
Address
After Reset
11100000b
11100000b
Function
0000h to FFFFh
Setting Range
After Reset
0000h
0000h
14. Timers
RW
RW
RW
RW
RW
RW
RW
RW
—