R5F212D8SNFP#U0 Renesas Electronics America, R5F212D8SNFP#U0 Datasheet - Page 354

• Manufacturer Part Number: R5F212D8SNFP#U0
• Description: IC R8C/2D MCU FLASH 64KB 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/2Dr

Specifications of R5F212D8SNFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• For Use With: R0K5212D8S001BE - KIT STARTER FOR R8C/2DR0K5212D8S000BE - KIT DEV FOR R8C/2D
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/2C Group, R8C/2D Group
Rev.2.00
REJ09B0339-0200
Figure 14.144 TRDOCR Register in PWM3 Mode
Timer RD Output Control Register
b7 b6 b5 b4
NOTES:
1.
2.
Write to the TRDOCR register w hen both bits TSTART0 and TSTART1 in the TRDSTR register are set to 0 (count
stops).
If the pin function is set for w aveform output (refer to Tables 14.27 and 14.28), the initial output level is output w hen
the TRDOCR register is set.
Dec 05, 2007
b3 b2
b1 b0
Bit Symbol
TRDOCR
Symbol
TOA0
TOB0
TOC0
TOD0
TOA1
TOB1
TOC1
TOD1
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TRDIOA0 output level select
bit
TRDIOB0 output level select
bit
TRDIOC0 initial output level
select bit
TRDIOD0 initial output level
select bit
TRDIOA1 initial output level
select bit
TRDIOB1 initial output level
select bit
TRDIOC1 initial output level
select bit
TRDIOD1 initial output level
select bit
(2)
(2)
(1)
Address
Bit Name
013Dh
0 : Active level “H”,
1 : Active level “L”,
0 : Active level “H”,
1 : Active level “L”,
These bits are disabled in PWM3 mode.
initial output “L”,
output “H” at compare match w ith the
TRDGRA1register,
output “L” at compare match w ith the
TRDGRA0 register
initial output “H”,
output “L” at compare match w ith the
TRDGRA1register,
output “H” at compare match w ith the
TRDGRA0 register
initial output “L”,
output “H” at compare match w ith the
TRDGRB1register,
output “L” at compare match w ith the
TRDGRB0 register
initial output “H”,
output “L” at compare match w ith the
TRDGRB1register,
output “H” at compare match w ith the
TRDGRB0 register
After Reset
Function
00h
14. Timers
RW
RW
RW
RW
RW
RW
RW
RW
RW