R5F212D8SNFP#U0 Renesas Electronics America, R5F212D8SNFP#U0 Datasheet - Page 498

• Manufacturer Part Number: R5F212D8SNFP#U0
• Description: IC R8C/2D MCU FLASH 64KB 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/2Dr

Specifications of R5F212D8SNFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• For Use With: R0K5212D8S001BE - KIT STARTER FOR R8C/2DR0K5212D8S000BE - KIT DEV FOR R8C/2D
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/2C Group, R8C/2D Group
Rev.2.00
REJ09B0339-0200
18. A/D Converter
The A/D converter consists of one 10-bit successive approximation A/D converter circuit with a capacitive coupling
amplifier. The analog input shares pins P0_0 to P0_7, P1_0 to P1_3, and P7_0 to P7_7.
Table 18.1 lists the Performance of A/D converter. Figure 18.1 shows a Block Diagram of A/D Converter.
Figures 18.2 and 18.4 show the A/D converter-related registers.
Table 18.1
NOTES:
A/D conversion method
Analog input voltage
Operating clock φAD
Resolution
Absolute accuracy
Operating mode
Analog input pin
A/D conversion start condition
Conversion rate per pin
1. The analog input voltage does not depend on use of a sample and hold function.
2. When 2.7 V ≤ AVCC ≤ 5.5 V, the frequency of φAD must be 10 MHz or below.
When the analog input voltage is over the reference voltage, the A/D conversion result will be 3FFh
in 10-bit mode and FFh in 8-bit mode.
When 2.2 V ≤ AVCC < 2.7 V, the frequency of φAD must be 5 MHz or below.
Without a sample and hold function, the φAD frequency should be 250 kHz or above.
With a sample and hold function, the φAD frequency should be 1 MHz or above.
Dec 05, 2007
Item
Performance of A/D converter
(1)
(2)
Page 475 of 585
Successive approximation (with capacitive coupling amplifier)
0 V to AVCC
4.2 V ≤ AVCC ≤ 5.5 V
2.2 V ≤ AVCC < 4.2 V
8 bits or 10 bits selectable
AVCC = Vref = 5 V, φAD = 10 MHz
AVCC = Vref = 3.3 V, φAD = 10 MHz
AVCC = Vref = 2.2 V, φAD = 5 MHz
One-shot mode, repeat mode 0, repeat mode 1, single sweep mode,
and repeat sweep mode
20 pins (AN0 to AN19)
• Software trigger
• Timer RD (complementary PWM mode)
• Without sample and hold function
• With sample and hold function
• 8-bit resolution
• 10-bit resolution ±3 LSB
• 8-bit resolution
• 10-bit resolution ±5 LSB
• 8-bit resolution
• 10-bit resolution ±5 LSB
Refer to 18.1.4 A/D Conversion Start Condition.
8-bit resolution: 49φAD cycles, 10-bit resolution: 59φAD cycles
8-bit resolution: 28φAD cycles, 10-bit resolution: 33φAD cycles
±2 LSB
±2 LSB
±2 LSB
f1, f2, f4, fOCO-F
f2, f4, fOCO-F
Performance
18. A/D Converter