R5F212D8SNFP#U0 Renesas Electronics America, R5F212D8SNFP#U0 Datasheet - Page 519

• Manufacturer Part Number: R5F212D8SNFP#U0
• Description: IC R8C/2D MCU FLASH 64KB 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/2Dr

Specifications of R5F212D8SNFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• For Use With: R0K5212D8S001BE - KIT STARTER FOR R8C/2DR0K5212D8S000BE - KIT DEV FOR R8C/2D
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/2C Group, R8C/2D Group
Rev.2.00
REJ09B0339-0200
20.2
Figure 20.1
The flash memory contains a user ROM area and a boot ROM area (reserved area). Figure 20.1 shows the Flash
Memory Block Diagram for R8C/2C Group. Figure 20.2 shows a Flash Memory Block Diagram for R8C/2D
Group.
The user ROM area of the R8C/2D Group contains an area (program ROM) which stores MCU operating programs
and blocks A and B (data flash) each 1 Kbyte in size.
The user ROM area is divided into several blocks. The user ROM area can be rewritten in CPU rewrite mode and
standard serial I/O and parallel I/O modes.
When rewriting blocks 0 and 1 in CPU rewrite mode, set the FMR02 bit in the FMR0 register to 1 (rewrite
enabled). When the FMR15 bit in the FMR1 register is set to 0 (rewrite enabled), block 0 is rewritable. When the
FMR16 bit is set to 0 (rewrite enabled), block 1 is rewritable. When rewriting blocks 2 and 3 in CPU rewrite mode,
FMR02 bit is set to 1 (rewrite enabled), blocks 2 and 3 are rewritable.
The rewrite control program for standard serial I/O mode is stored in the boot ROM area before shipment. The boot
ROM area and the user ROM area share the same address, but have separate memory areas.
Memory Map
0BFFFh
0FFFFh
0BFFFh
0FFFFh
1BFFFh
0C000h
0C000h
13FFFh
1C000h
23FFFh
04000h
04000h
10000h
14000h
Dec 05, 2007
NOTES:
1. When the FMR02 bit in the FMR0 register is set to 1 (rewrite enabled) and the FMR15 bit in the FMR1 register is set to 0 (rewrite enabled),
2. When the FMR02 bit in the FMR0 register is set to 1 (rewrite enabled), blocks 2 and 3 are rewritable (only for CPU rewrite mode).
3. The emulator debugger cannot be used by address 20000h to 23FFFh. Refer to 24. Notes on Emulator Debugger.
4. This area is for storing the boot program provided by Renesas Technology.
block 0 is rewritable. When the FMR16 bit is set to 0 (rewrite enabled), block 1 is rewritable (only for CPU rewrite mode).
128 Kbytes ROM product
48 Kbytes ROM product
Block 3: 32 Kbytes
Block 0: 16 Kbytes
Block 1: 32 Kbytes
Block 1: 32 Kbytes
Block 0: 32 Kbytes
Block 2: 32 Kbytes
Flash Memory Block Diagram for R8C/2C Group
User ROM area
User ROM area
Page 496 of 585
(2, 3)
(1)
(1)
(2)
(1)
(1)
0BFFFh
0FFFFh
0C000h
13FFFh
04000h
10000h
Program
ROM
64 Kbytes ROM product
Block 1: 32 Kbytes
Block 0: 32 Kbytes
User ROM area
(1)
(1)
0BFFFh
0FFFFh
1BFFFh
0C000h
13FFFh
04000h
10000h
14000h
96 Kbytes ROM product
Block 1: 32 Kbytes
Block 0: 32 Kbytes
Block 2: 32 Kbytes
User ROM area
(1)
(1)
(2)
Program
ROM
0FFFFh
0E000h
(reserved area)
Boot ROM area
8 Kbytes
20. Flash Memory
(4)