R5F212D8SNFP#U0 Renesas Electronics America, R5F212D8SNFP#U0 Datasheet - Page 411

• Manufacturer Part Number: R5F212D8SNFP#U0
• Description: IC R8C/2D MCU FLASH 64KB 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/2Dr

Specifications of R5F212D8SNFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• For Use With: R0K5212D8S001BE - KIT STARTER FOR R8C/2DR0K5212D8S000BE - KIT DEV FOR R8C/2D
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/2C Group, R8C/2D Group
Rev.2.00
REJ09B0339-0200
Figure 15.10
Figure 15.11
15.1.1
15.1.2
the transfer clock polarity.
Figure 15.11 shows the Transfer Format. Use the UFORM bit in the UiC0 (i = 0 to 2) register to select the
transfer format.
Figure 15.10 shows the Transfer Clock Polarity. Use the CKPOL bit in the UiC0 (i = 0 to 2) register to select
Dec 05, 2007
Polarity Select Function
LSB First/MSB First Select Function
Transfer Clock Polarity
Transfer Format
• When the CKPOL bit in the UiC0 register = 0 (output transmit data at the falling
CLKi
• When the CKPOL bit in the UiC0 register = 1 (output transmit data at the rising
CLKi
• When UFORM bit in UiC0 register = 0 (LSB first)
• When UFORM bit in UiC0 register = 1 (MSB first)
RXDi
RXDi
TXDi
TXDi
RXDi
RXDi
CLKi
CLKi
TXDi
TXDi
edge and input receive data at the rising edge of the transfer clock)
edge and input receive data at the falling edge of the transfer clock)
NOTES:
NOTE:
i = 0 to 2
i = 0 to 2
(1)
(2)
1. When not transferring, the CLKi pin level is “H”.
2. When not transferring, the CLKi pin level is “L”.
1. The above applies when the CKPOL bit in the UiC0 register is
set to 0 (output transmit data at the falling edge and input receive
data at the rising edge of the transfer clock).
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D0
D0
D0
D0
D0
D0
D7
D7
D1
D1
D1
D1
D1
D1
D6
D6
D2
D2
D2
D2
D2
D2
D5
D5
D3
D3
D4
D4
D3
D3
D3
D3
(1)
D4
D4
D4
D4
D4
D4
D3
D3
(1)
D5
D5
D5
D5
D5
D5
D2
D2
D6
D6
D6
D6
D6
D6
D1
D1
D7
D7
D7
D7
D7
D7
D0
D0
15. Serial Interface