R5F212D8SNFP#U0 Renesas Electronics America, R5F212D8SNFP#U0 Datasheet - Page 407

• Manufacturer Part Number: R5F212D8SNFP#U0
• Description: IC R8C/2D MCU FLASH 64KB 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/2Dr

Specifications of R5F212D8SNFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• For Use With: R0K5212D8S001BE - KIT STARTER FOR R8C/2DR0K5212D8S000BE - KIT DEV FOR R8C/2D
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/2C Group, R8C/2D Group
Rev.2.00
REJ09B0339-0200
15.1
Table 15.1
i = 0 to 2
NOTES:
Transfer data format
Transfer clocks
Transmit start conditions
Receive start conditions
Interrupt request
generation timing
Error detection
Select functions
In clock synchronous serial I/O mode, data is transmitted and received using a transfer clock.
Table 15.1 lists the Clock Synchronous Serial I/O Mode Specifications. Table 15.2 lists the Registers Used and
Settings in Clock Synchronous Serial I/O Mode
1. If an external clock is selected, ensure that the external clock is “H” when the CKPOL bit in the UiC0
2. If an overrun error occurs, the receive data (b0 to b8) of the UiRB register will be undefined. The IR
register is set to 0 (transmit data output at falling edge and receive data input at rising edge of
transfer clock), and that the external clock is “L” when the CKPOL bit is set to 1 (transmit data output
at rising edge and receive data input at falling edge of transfer clock).
bit in the SiRIC register remains unchanged.
Clock Synchronous Serial I/O Mode
Dec 05, 2007
Item
Clock Synchronous Serial I/O Mode Specifications
Page 384 of 585
• Transfer data length: 8 bits
• CKDIR bit in UiMR register is set to 0 (internal clock): fi/(2(n+1))
• The CKDIR bit is set to 1 (external clock): input from CLKi pin
• Before transmission starts, the following requirements must be met
• Before reception starts, the following requirements must be met
• When transmitting, one of the following conditions can be selected
• When receiving
• Overrun error
• CLK polarity selection
• LSB first, MSB first selection
• Continuous receive mode selection
fi = f1, f8, f32 n = value set in UiBRG register: 00h to FFh
- The TE bit in the UiC1 register is set to 1 (transmission enabled)
- The TI bit in the UiC1 register is set to 0 (data in the UiTB register)
- The RE bit in the UiC1 register is set to 1 (reception enabled)
- The TE bit in the UiC1 register is set to 1 (transmission enabled)
- The TI bit in the UiC1 register is set to 0 (data in the UiTB register)
- The UiIRS bit is set to 0 (transmit buffer empty):
- The UiIRS bit is set to 1 (transmission completes):
When data transfer from the UARTi receive register to the UiRB register
(when reception completes).
This error occurs if the serial interface starts receiving the next data item
before reading the UiRB register and receives the 7th bit of the next data.
Transfer data input/output can be selected to occur synchronously with the
rising or the falling edge of the transfer clock.
Whether transmitting or receiving data begins with bit 0 or begins with bit 7
can be selected.
Receive is enabled immediately by reading the UiRB register.
When transferring data from the UiTB register to UARTi transmit register
(when transmission starts).
When completing data transmission from UARTi transmit register.
(2)
(1)
.
Specification
15. Serial Interface
(1)
(1)