R5F212D8SNFP#U0 Renesas Electronics America, R5F212D8SNFP#U0 Datasheet - Page 391

• Manufacturer Part Number: R5F212D8SNFP#U0
• Description: IC R8C/2D MCU FLASH 64KB 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/2Dr

Specifications of R5F212D8SNFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• For Use With: R0K5212D8S001BE - KIT STARTER FOR R8C/2DR0K5212D8S000BE - KIT DEV FOR R8C/2D
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/2C Group, R8C/2D Group
Rev.2.00
REJ09B0339-0200
Figure 14.179 TRFCR1 Register
Figure 14.180 TRFOUT Register
Timer RF Output Control Register
Timer RF Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0
b7 b6 b5 b4
NOTES:
1.
2.
3.
4.
If filter enabled, w hen the same value from the TRFI pin is sampled three times continuously, the input is determined.
When the TMOD bit is set to 0 (input capture mode), set bits CCLR, and TRFC14 to TRFC17 to 0.
When the TSTART bit in the TRFCR0 register is set to 0 (count stops), rew rite bits CCLR and TMOD.
When the TMOD bit is set to 0 (input capture mode), set bits ILVL2 to ILVL0 in the CMP1IC register to 000b (level 0)
and set the IR bit to 0 (no interrupt requested).
Dec 05, 2007
b3 b2
b1 b0
Bit Symbol
Bit Symbol
TRFOUT0
TRFOUT1
TRFOUT2
TRFOUT3
TRFOUT4
TRFOUT5
TRFOUT6
TRFOUT7
TRFOUT
TRFCR1
TRFC14
TRFC15
TRFC16
TRFC17
Symbol
Symbol
TMOD
CCLR
TIPF0
TIPF1
Page 368 of 585
TRFO00 output enable bit
TRFO01 output enable bit
TRFO02 output enable bit
TRFO10 output enable bit
TRFO11 output enable bit
TRFO12 output enable bit
TRFO00 to TRFO02 output invert
bit
TRFO10 to TRFO12 output invert
bit
TRFI filter select bits
TRF register count operation
select bit
Timer RF operation mode
select bit
Compare 0 output select
bits
Compare 1 output select
bits
(2)
(2)
(2, 3)
(3)
Address
Bit Name
029Bh
Address
Bit Name
02FFh
(1)
b1 b0
0 0 : No filter
0 1 : Filter w ith f1 sampling
1 0 : Filter w ith f8 sampling
1 1 : Filter w ith f32 sampling
b5 b4
0 0 : Unchanged
0 1 : Inverted
1 0 : “L”
1 1 : “H”
b7 b6
0 0 : Unchanged
0 1 : Inverted
1 0 : “L”
1 1 : “H”
0 : Free-running operation
1 : Set TRF register to 0000h w hen compare
0 : Input capture mode
1 : Output compare mode
1 is matched.
CMP output w hen compare 0 is matched
CMP output w hen compare 0 is matched
0 : Output disabled
1 : Output enabled
0 : Output not inverted
1 : Output inverted
After Reset
Function
(2, 4)
After Reset
00h
Function
00h
14. Timers
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW