R5F212D8SNFP#U0 Renesas Electronics America, R5F212D8SNFP#U0 Datasheet - Page 404

• Manufacturer Part Number: R5F212D8SNFP#U0
• Description: IC R8C/2D MCU FLASH 64KB 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/2Dr

Specifications of R5F212D8SNFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• For Use With: R0K5212D8S001BE - KIT STARTER FOR R8C/2DR0K5212D8S000BE - KIT DEV FOR R8C/2D
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/2C Group, R8C/2D Group
Rev.2.00
REJ09B0339-0200
Figure 15.5
UARTi Transmit Buffer Register (i = 0 to 2)
UARTi Transmit/Receive Control Register 0 (i = 0 to 2)
(b15)
b7
NOTES:
b7 b6 b5 b4
NOTE:
1.
2.
1.
When the transfer data length is 9 bits, w rite data to high byte first, then low byte.
Use the MOV instruction to w rite to this register.
If the BRG count source is sw itched, set the UiBRG register again.
Dec 05, 2007
b3 b2
0
Registers U0TB to U2TB and U0C0 to U2C0
b1 b0
(b8)
b0
b7
Bit Symbol
(b15-b9)
(b8-b0)
UFORM
Symbol
CKPOL
TXEPT
U0C0
U1C0
U2C0
CLK0
CLK1
NCH
(b2)
(b4)
Page 381 of 585
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—
—
—
BRG count source select
bits
Reserved bit
Transmit register empty
flag
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Data output select bit
CLK polarity select bit
Transfer format select bit 0 : LSB first
Transmit data
Nothing is assigned. If necessary, set to 0.
When read, the content is undefined.
b0
(1)
Symbol
Address
Bit Name
U0TB
U1TB
U2TB
00A4h
00ACh
0164h
(1, 2)
b1 b0
0 0 : Selects f1
0 1 : Selects f8
1 0 : Selects f32
1 1 : Do not set.
Set to 0.
0 : Data in transmit register (during transmit)
1 : No data in transmit register (transmit completed)
0 : TXDi pin is for CMOS output
1 : TXDi pin is for N-channel open-drain output
0 : Transmit data is output at falling edge of transfer
1 : Transmit data is output at rising edge of transfer
1 : MSB first
Function
clock and receive data is input at rising edge
clock and receive data is input at falling edge
00ABh-00AAh
00A3h-00A2h
0163h-0162h
Address
After Reset
00001000b
00001000b
00001000b
Function
After Reset
Undefined
Undefined
Undefined
15. Serial Interface
WO
RW
RW
RW
RW
RW
RW
RW
RW
—
RO
—