R5F212D8SNFP#U0 Renesas Electronics America, R5F212D8SNFP#U0 Datasheet - Page 481

• Manufacturer Part Number: R5F212D8SNFP#U0
• Description: IC R8C/2D MCU FLASH 64KB 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/2Dr

Specifications of R5F212D8SNFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• For Use With: R0K5212D8S001BE - KIT STARTER FOR R8C/2DR0K5212D8S000BE - KIT DEV FOR R8C/2D
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/2C Group, R8C/2D Group
Rev.2.00
REJ09B0339-0200
Figure 16.51
16.3.7
Table 16.8
1Tcyc = 1/f1(s)
When setting the I
two cases:
Therefore, the SCL signal is monitored and communication is synchronized bit by bit.
Figure 16.51 shows the Timing of Bit Synchronization Circuit and Table 16.8 lists the Time between Changing
SCL Signal from “L” Output to High-Impedance and Monitoring of SCL Signal.
•
•
Dec 05, 2007
If the SCL signal is driven L level by a slave device
If the rise speed of the SCL signal is reduced by a load (load capacity or pull-up resistor) on the SCL line.
Bit Synchronization Circuit
CKS3
0
1
Timing of Bit Synchronization Circuit
Time between Changing SCL Signal from “L” Output to High-Impedance and
Monitoring of SCL Signal
ICCR1 Register
SCL monitor timing
2
Reference clock of
C bus interface to master mode, the high-level period may become shorter in the following
Page 458 of 585
Internal SCL
SCL
CKS2
0
1
0
1
VIH
7.5Tcyc
19.5Tcyc
17.5Tcyc
41.5Tcyc
Time for Monitoring SCL
16. Clock Synchronous Serial Interface