R5F212D8SNFP#U0 Renesas Electronics America, R5F212D8SNFP#U0 Datasheet - Page 324

• Manufacturer Part Number: R5F212D8SNFP#U0
• Description: IC R8C/2D MCU FLASH 64KB 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/2Dr

Specifications of R5F212D8SNFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• For Use With: R0K5212D8S001BE - KIT STARTER FOR R8C/2DR0K5212D8S000BE - KIT DEV FOR R8C/2D
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/2C Group, R8C/2D Group
Rev.2.00
REJ09B0339-0200
Figure 14.116 Registers TRDSTR and TRDMR in Reset Synchronous PWM Mode
Timer RD Start Register
Timer RD Mode Register
b7 b6 b5 b4 b3 b2
NOTES:
b7 b6 b5 b4
1.
2.
3.
4.
5.
Set the TRDSTR register using the MOV instruction (do not use the bit handling instruction). Refer to 14.4.12.1
TRDSTR Register of Notes on Tim er RD .
When the CSEL0 bit is set to 1, w rite 0 to the TSTART0 bit.
When the CSEL1 bit is set to 1, w rite 0 to the TSTART1 bit.
When the CSEL0 bit is set to 0 and the compare match signal (TRDIOA0) is generated, this bit is set to 0 (count
stops).
When the CSEL1 bit is set to 0 and the compare match signal (TRDIOA1) is generated, this bit is set to 0 (count
stops).
Dec 05, 2007
b3 b2
b1 b0
b1 b0
0
Bit Symbol
Bit Symbol
TSTART0
TSTART1
TRDSTR
(b7-b4)
(b3-b1)
Symbol
Symbol
TRDMR
CSEL0
CSEL1
SYNC
BFC0
BFD0
BFC1
BFD1
(1)
Page 301 of 585
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TRD0 count start flag
TRD1 count start flag
TRD0 count operation select bit 0 : Count stops at the compare match w ith
TRD1 count operation select bit 0 : Count stops at the compare match w ith
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
Timer RD synchronous bit
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
TRDGRC0 register function select
bit
TRDGRD0 register function select
bit
TRDGRC1 register function select
bit
TRDGRD1 register function select
bit
Address
Bit Name
Address
Bit Name
0137h
0138h
(4)
(5)
0 : Count stops
1 : Count starts
0 : Count stops
1 : Count starts
1 : Count continues after the compare
1 : Count continues after the compare
Set this bit to 0 (registers TRD0 and TRD1
operate independently) in reset synchronous
PWM mode.
0 : General register
1 : Buffer register of TRDGRA0 register
0 : General register
1 : Buffer register of TRDGRB0 register
0 : General register
1 : Buffer register of TRDGRA1 register
0 : General register
1 : Buffer register of TRDGRB1 register
the TRDGRA0 register
match w ith the TRDGRA0 register
the TRDGRA1 register
match w ith the TRDGRA1 register
(2)
(3)
After Reset
11111100b
After Reset
00001110b
Function
Function
14. Timers
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
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