R5F212D8SNFP#U0 Renesas Electronics America, R5F212D8SNFP#U0 Datasheet - Page 586

• Manufacturer Part Number: R5F212D8SNFP#U0
• Description: IC R8C/2D MCU FLASH 64KB 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/2Dr

Specifications of R5F212D8SNFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• For Use With: R0K5212D8S001BE - KIT STARTER FOR R8C/2DR0K5212D8S000BE - KIT DEV FOR R8C/2D
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/2C Group, R8C/2D Group
Rev.2.00
REJ09B0339-0200
Figure 22.4
TRDGRB0 register
TRDGRA1 register
TRDGRB1 register
TRDSR0 register
Count value in TRD0
IMFA bit in
Setting value in
•
Dec 05, 2007
If the value in the TRDGRA0 register is assumed to be m, the TRD0 register counts m-1, m, m+1, m, m-1,
in that order, when changing from increment to decrement operation.
When changing from m to m+1, the IMFA bit is set to 1. Also, bits CMD1 to CMD0 in the TRDFCR
register are set to 11b (complementary PWM mode, buffer data transferred at compare match between
registers TRD0 and TRDGRA0), the content in the buffer registers (TRDGRD0, TRDGRC1, and
TRDGRD1) is transferred to the general registers (TRDGRB0, TRDGRA1, and TRDGRB1).
During m+1, m, and m-1 operation, the IMFA bit remains unchanged and data are not transferred to
registers such as the TRDGRA0 register.
register m
TRDGRA0
Operation at Compare Match between Registers TRD0 and TRDGRA0 in
Complementary PWM Mode
register
1
0
Set to 0 by a program
Page 563 of 585
Transferred from
buffer register
m+1
No change
Not transferred from buffer register
When bits CMD1 to CMD0 in the
TRDFCR register are set to 11b
(transfer from the buffer register to the
general register at compare match of
between registers TRD0 and
TRDGRA0).
22. Usage Notes