R5F212D8SNFP#U0 Renesas Electronics America, R5F212D8SNFP#U0 Datasheet - Page 159

• Manufacturer Part Number: R5F212D8SNFP#U0
• Description: IC R8C/2D MCU FLASH 64KB 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/2Dr

Specifications of R5F212D8SNFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• For Use With: R0K5212D8S001BE - KIT STARTER FOR R8C/2DR0K5212D8S000BE - KIT DEV FOR R8C/2D
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/2C Group, R8C/2D Group
Rev.2.00
REJ09B0339-0200
Figure 12.8
Figure 12.9
Address
12.1.6.7
m−4
m−3
m−2
m−1
m+1
m
Stack state before interrupt request
is acknowledged
In the interrupt sequence, the FLG register and PC are saved to the stack.
After an extended 16 bits, 4 high-order bits in the PC and 4 high-order (IPL) and 8 low-order bits in the FLG
register, are saved to the stack, the 16 low-order bits in the PC are saved.
Figure 12.8 shows the Stack State Before and After Acknowledgement of Interrupt Request.
The other necessary registers are saved by a program at the beginning of the interrupt routine. The PUSHM
instruction can save several registers in the register bank being currently used
NOTE:
The register saving operation, which is performed as part of the interrupt sequence, saved in 8 bits at a time in
four steps.
Figure 12.9 shows the Register Saving Operation.
MSB
Previous stack contents
Previous stack contents
Dec 05, 2007
1. Selectable from registers R0, R1, R2, R3, A0, A1, SB, and FB.
Saving a Register
Stack
Stack State Before and After Acknowledgement of Interrupt Request
Register Saving Operation
NOTE:
Address
NOTE:
[SP]−5
[SP]−4
[SP]−3
[SP]−2
[SP]−1
1.When executing software number 32 to 63 INT instructions,
1. [SP] indicates the initial value of the SP when an interrupt request is acknowledged.
[SP]
this SP is specified by the U flag. Otherwise it is ISP.
software number 32 to 63 INT instructions, this SP is specified by the U
flag. Otherwise it is ISP.
After registers are saved, the SP content is [SP] minus 4.
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FLGH
LSB
Stack
PCM
FLGL
PCL
[SP]
SP value before
interrupt is generated
PCH
Sequence in which
order registers are
saved
Completed saving
registers in four
operations.
(3)
(4)
(1)
(2)
Saved, 8 bits at a time
Address
m+1
m−4
m−3
m−2
m−1
m
When executing
Stack state after interrupt request
is acknowledged
MSB
Previous stack contents
Previous stack contents
FLGH
FLGL
PCM
PCL
Stack
PCH
PCM
PCL
FLGH
FLGL
PCH
: 4 high-order bits of PC
: 8 middle-order bits of PC
: 8 low-order bits of PC
: 4 high-order bits of FLG
: 8 low-order bits of FLG
(1)
LSB
with a single instruction.
PCH
PCM
PCL
FLGH
FLGL
[SP]
New SP value
: 4 high-order bits of PC
: 8 middle-order bits of PC
: 8 low-order bits of PC
: 4 high-order bits of FLG
: 8 low-order bits of FLG
12. Interrupts