R5F212D8SNFP#U0 Renesas Electronics America, R5F212D8SNFP#U0 Datasheet - Page 168

• Manufacturer Part Number: R5F212D8SNFP#U0
• Description: IC R8C/2D MCU FLASH 64KB 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/2Dr

Specifications of R5F212D8SNFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• For Use With: R0K5212D8S001BE - KIT STARTER FOR R8C/2DR0K5212D8S000BE - KIT DEV FOR R8C/2D
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/2C Group, R8C/2D Group
Rev.2.00
REJ09B0339-0200
12.4
Table 12.6
NOTES:
Table 12.7
• Instruction with 2-byte operation code
• Instruction with 1-byte operation code
ADD.B:S
OR.B:S
STNZ
CMP.B:S
JMPS
MOV.B:S
• Instructions other than the above
Address match interrupt 0
Address match interrupt 1
Address Match Interrupt Source Address Match Interrupt Enable Bit Address Match Interrupt Register
An address match interrupt request is generated immediately before execution of the instruction at the address
indicated by the RMADi register (i = 0 or 1). This interrupt is used as a break function by the debugger. When
using the on-chip debugger, do not set an address match interrupt (registers of AIER, RMAD0, and RMAD1 and
fixed vector tables) in a user system.
Set the starting address of any instruction in the RMADi register. Bits AIER0 and AIER1 in the AIER0 register can
be used to select enable or disable of the interrupt. The I flag and IPL do not affect the address match interrupt.
The value of the PC (Refer to 12.1.6.7 Saving a Register for the value of the PC) which is saved to the stack when
an address match interrupt is acknowledged varies depending on the instruction at the address indicated by the
RMADi register. (The appropriate return address is not saved on the stack.) When returning from the address match
interrupt, return by one of the following means:
Table 12.6 lists the Values of PC Saved to Stack when Address Match Interrupt is Acknowledged.
Figure 12.20 shows Registers AIER and RMAD0 to RMAD1.
1. Refer to the 12.1.6.7 Saving a Register for the PC value saved.
2. Operation code: Refer to the R8C/Tiny Series Software Manual (REJ09B0001).
•
•
Change the content of the stack and use the REIT instruction.
Use an instruction such as POP to restore the stack as it was before the interrupt request was acknowledged.
Then use a jump instruction.
Address Match Interrupt
Dec 05, 2007
#IMM8,dest SUB.B:S
#IMM8,dest MOV.B:S #IMM8,dest STZ
#IMM8,dest STZX
#IMM8,dest PUSHM
#IMM8
#IMM,dest (however, dest = A0 or A1)
Values of PC Saved to Stack when Address Match Interrupt is Acknowledged
Correspondence Between Address Match Interrupt Sources and Associated Registers
Address Indicated by RMADi Register (i = 0 or 1)
Chapter 4. Instruction Code/Number of Cycles contains diagrams showing
operation code below each syntax. Operation code is shown in the bold frame in
the diagrams.
Page 145 of 585
JSRS
AIER0
AIER1
#IMM8,dest AND.B:S
#IMM81,#IMM82,dest
src
#IMM8
(2)
(2)
POPM
#IMM8,dest
#IMM8,dest
dest
RMAD0
RMAD1
Address indicated by
RMADi register + 2
Address indicated by
RMADi register + 1
PC Value Saved
12. Interrupts
(1)