MCF5307AI90B Freescale Semiconductor, MCF5307AI90B Datasheet - Page 114

• Manufacturer Part Number: MCF5307AI90B
• Description: IC MPU 32BIT COLDF 90MHZ 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307AI90B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 90MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 90 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 90MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: FQFP
• Program Memory Size: 8KB
• Cpu Speed: 90MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Cache Operation
4.9.3.2 Write Miss
The cache controller handles processor writes that miss in the cache differently for
write-through and copyback regions. Write misses to copyback regions cause the cache line
to be read from system memory, as shown in Figure 4-6.
The new cache line is then updated with write data and the M bit is set for the line, leaving
it in modified state. Write misses to write-through regions write directly to memory without
loading the corresponding cache line into the cache.
4.9.3.3 Read Hit
On a read hit, the cache provides the data to the processor core and the cache line state
remains unchanged. If the cache mode changes for a specific region of address space, lines
in the cache corresponding to that region that contain modified data are not pushed out to
memory when a read hit occurs within that line. First execute a CPUSHL instruction or set
CACR[CINVA] before switching the cache mode.
4.9.3.4 Write Hit
The cache controller handles processor writes that hit in the cache differently for
write-through and copyback regions. For write hits to a write-through region, portions of
cache lines corresponding to the size of the access are updated with the data. The data is
1. Writing character X to 0x0B generates a write miss. Data cannot be written to an invalid line.
4-16
2. The cache line (characters A–P) is updated from system memory, and line is marked valid.
3. After the cache line is filled, the write that initiated the write miss (the character X) completes to 0x0B.
MCF5307
MCF5307
Figure 4-6. Write-Miss in Copyback Mode
Freescale Semiconductor, Inc.
For More Information On This Product,
X
ABCD EFGH IJKL MNOP
ABCD EXGH IJKL MNOP
0x0C
0x0C
0x0C
Go to: www.freescale.com
MCF5307 User’s Manual
0x08 0x04
0x08 0x04
0x08 0x04
Cache Line
0x00
0x00
0x00
M = 0
V = 0
M = 0
V = 1
M = 1
V = 1
Memory
System