MCF5307AI90B Freescale Semiconductor, MCF5307AI90B Datasheet - Page 225

• Manufacturer Part Number: MCF5307AI90B
• Description: IC MPU 32BIT COLDF 90MHZ 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307AI90B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 90MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 90 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 90MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: FQFP
• Program Memory Size: 8KB
• Cpu Speed: 90MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Chapter 10
Chip-Select Module
This chapter describes the MCF5307 chip-select module, including the operation and
programming model of the chip-select registers, which include the chip-select address,
mask, and control registers.
10.1 Overview
The following list summarizes the key chip-select features:
10.2 Chip-Select Module Signals
Table 10-1 lists signals used by the chip-select module.
Table 10-2 shows the interaction of the byte enable/byte-write enables with related signals.
Chip Selects
(CS[7:0])
Output
Enable (OE)
Byte Enables/
Byte Write
Enables
(BE[3:0]/
BWE[3:0])
• Eight independent, user-programmable chip-select signals (CS[7:0]) that can
• Address masking for 64-Kbyte to 4-Gbyte memory block sizes
• Programmable wait states and port sizes
• External master access to chip selects
Signal
interface with SRAM, PROM, EPROM, EEPROM, Flash, and peripherals
Each CSn can be independently programmed for an address location as well as for masking, port
size, read/write burst-capability, wait-state generation, and internal/external termination. Only CS0
is initialized at reset when it acts as a global chip select that allows boot ROM to be at any defined
address space. Port size and termination (internal versus external) and byte enables for CS0 are
configured by the logic levels of D[7:5] when RSTI negates.
Interfaces to memory or to peripheral devices and enables a read transfer. It is asserted and
negated on the falling edge of the clock. OE is asserted only when one of the chip selects matches
for the current address decode.
These multiplexed signals are individually programmed through the byte enable mode bit,
CSCRn[BEM], described in Section 10.4.1.3, “Chip-Select Control Registers (CSCR0–CSCR7).”
These generated signals provide byte data select signals, which are decoded from the transfer
size, A1, and A0 signals in addition to the programmed port size and burstability of the memory
accessed, as Table 10-2 shows.
Freescale Semiconductor, Inc.
Table 10-1. Chip-Select Module Signals
For More Information On This Product,
Chapter 10. Chip-Select Module
Go to: www.freescale.com
Description
10-1