MCF5307AI90B Freescale Semiconductor, MCF5307AI90B Datasheet - Page 263

• Manufacturer Part Number: MCF5307AI90B
• Description: IC MPU 32BIT COLDF 90MHZ 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307AI90B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 90MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 90 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 90MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: FQFP
• Program Memory Size: 8KB
• Cpu Speed: 90MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Accesses in synchronous burst page mode always cause the following sequence:
11.4.4.4 Continuous Page Mode
Continuous page mode is identical to burst page mode, except that it allows the processor
core to handle successive bus cycles that hit the same page without having to close the page.
When the current bus cycle finishes, the MCF5307 core internal pipelined bus can predict
whether the upcoming cycle will hit in the same page.
RAS[0] or [1]
1.
2.
3. Required number of
4. Some transfers need more
5.
6. Required number of idle clocks inserted to assure precharge-to-
• If the next bus cycle is not pending or misses in the page, the
• If the next bus cycle is pending and hits in the page, the page is left open, and the
CAS[3:0]
DRAMW
BCLKO
D[31:0]
A[31:0]
SRAS
SCAS
ACTV
NOP
NOP
given port size.
PALL
generated to the SDRAM.
next SDRAM access begins with a
commands to assure SRAS-to-SCAS delay (if CAS latency is 1, there are no
commands).
command
command
ACTV
t
CASL
Chapter 11. Synchronous/Asynchronous DRAM Controller Module
Row
= 2
NOP
Figure 11-19. Burst Write SDRAM Access
Freescale Semiconductor, Inc.
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READ
Column
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or
NOP
WRITE
commands to assure the
Column
WRITE
READ
commands to service the transfer size with the
Column
or
WRITE
t
RWL
command.
NOP
Column
ACTV
PALL
-to-precharge delay.
Synchronous Operation
PALL
ACTV
t
command is
RP
delay.
11-29