MCF5307AI90B Freescale Semiconductor, MCF5307AI90B Datasheet - Page 471

• Manufacturer Part Number: MCF5307AI90B
• Description: IC MPU 32BIT COLDF 90MHZ 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307AI90B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 90MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 90 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 90MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: FQFP
• Program Memory Size: 8KB
• Cpu Speed: 90MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

L
L
M
Implementation. A particular processor that conforms to the ColdFire
Imprecise mode. A memory access mode that allows write accesses to a
Instruction queue. A holding place for instructions fetched from the current
Instruction latency. The total number of clock cycles necessary to execute
Interrupt. An asynchronous exception. On ColdFire processors, interrupts
Invalid state. State of a cache entry that does not currently contain a valid
Least-significant bit (lsb). The bit of least value in an address, register, data
Least-significant byte (LSB). The byte of least value in an address, register,
Longword. A 32-bit data element
Master. A device able to initiate data transfers on a bus. Bus mastering refers
Memory coherency. An aspect of caching in which it is ensured that an
Modified state. Cache state in which only one caching device has the valid
Most-significant bit (msb). The highest-order bit in an address, registers,
Most-significant byte (MSB). The highest-order byte in an address,
architecture, but may differ from other architecture-compliant
implementations for example in design, feature set, and
implementation of optional features. The ColdFire architecture has
many different implementations.
specified memory region to occur out of order.
instruction stream.
an instruction and make the results of that instruction available.
are a special case of exceptions. See also asynchronous exception.
copy of a cache line from memory.
element, or instruction encoding.
data element, or instruction encoding.
to a feature supported by some bus architectures that allow a
controller connected to the bus to communicate directly with other
devices on the bus without going through the CPU.
accurate view of memory is provided to all devices that share system
memory.
data for that address.
data element, or instruction encoding.
registers, data element, or instruction encoding.
Freescale Semiconductor, Inc.
For More Information On This Product,
Glossary of Terms and Abbreviations
Go to: www.freescale.com
Glossary-13