MCF5307AI90B Freescale Semiconductor, MCF5307AI90B Datasheet - Page 407

• Manufacturer Part Number: MCF5307AI90B
• Description: IC MPU 32BIT COLDF 90MHZ 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307AI90B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 90MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 90 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 90MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: FQFP
• Program Memory Size: 8KB
• Cpu Speed: 90MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

18.7.2 Interrupt-Acknowledge Cycle
When the MCF5307 processes an interrupt exception, it performs an interrupt-
acknowledge bus cycle to obtain the vector number that contains the starting location of the
interrupt exception handler. The interrupt-acknowledge bus cycle is a read transfer that
differs from normal read cycles in the following respects:
During the interrupt-acknowledge bus cycle (a read cycle), the responding device places the
vector number on D[31:24] and the cycle is terminated normally with TA. Figure 18-23 is
a flow diagram for an interrupt-acknowledge cycle terminated with TA.
• The interrupt request on the interrupt control pins is raised to level 7 and stays there
• The interrupt request on the interrupt control pins is raised to level 7 and stays there.
• TT[1:0] = 0x3 to indicate a CPU space or acknowledge bus cycle.
• TM[2:0] = the level of interrupt being acknowledged.
• A[31:5] = 0x7F_FFFF.
• A[4:2] = the interrupt request level being acknowledged (same as TM[2:0]).
• A[1:0] = 00.
until an interrupt-acknowledge cycle begins. The level later drops but then returns to
level 7, causing a second transition on the interrupt control lines.
If the level 7 interrupt routine lowers the mask level, a second level 7 interrupt is
recognized without a transition of the interrupt control pins. After the level 7 routine
completes, the MCF5307 compares the mask level to the request level on the IRQx
signals. Because the mask level is lower than the requested level, the interrupt mask
is set back to level 7. To ensure it is recognized, the level 7 request on IRQ7 must be
held until the second interrupt-acknowledge bus cycle begins.
Freescale Semiconductor, Inc.
For More Information On This Product,
Chapter 18. Bus Operation
Go to: www.freescale.com
Interrupt Exceptions
18-19