MCF5307AI90B Freescale Semiconductor, MCF5307AI90B Datasheet - Page 435

• Manufacturer Part Number: MCF5307AI90B
• Description: IC MPU 32BIT COLDF 90MHZ 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307AI90B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 90MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 90 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 90MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: FQFP
• Program Memory Size: 8KB
• Cpu Speed: 90MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

19.6 Disabling IEEE Standard 1149.1 Operation
There are two ways to use the MCF5307 without IEEE Standard 1149.1 test logic being
active:
• Nonuse of JTAG test logic by either nontermination (disconnection) or intentionally
• Disabling JTAG test logic by holding MTMOD0 low during reset (debug mode).
fixing TAP logic values. The following issues must be addressed if IEEE Standard
1149.1 logic is not to be used when the MCF5307 is assembled onto a board.
— IEEE Standard 1149.1 test logic must remain transparent and benign to the
— TCK has no internal pull-up as is required on TMS, TDI, and TRST; therefore,
This allows the IEEE Standard 1149.1 test controller to enter test-logic-reset state
when TRST is internally asserted to the controller. TAP pins function as debug mode
pins. In JTAG mode, inputs TDI/DSI, TMS/BKPT, and TRST/DSCLK have internal
pull-ups enabled. Figure 19-5 shows pin values recommended for disabling JTAG in
debug mode.
system logic during functional operation. To ensure that the part enters the
test-logic-reset state requires either connecting TRST to logic 0 or connecting
TCK to a source that supplies five rising edges and a falling edge after the fifth
rising edge. The recommended solution is to connect TRST to logic 0.
it must be terminated to preclude mid-level input values. Figure 19-4 shows pin
values recommended for disabling JTAG with the MCF5307 in JTAG mode.
Figure 19-5. Disabling JTAG in Debug Mode
Figure 19-4. Disabling JTAG in JTAG Mode
Chapter 19. IEEE 1149.1 Test Access Port (JTAG)
Freescale Semiconductor, Inc.
For More Information On This Product,
Debug Interface
Note: MTMOD0 high allows JTAG mode.
Go to: www.freescale.com
Note: MTMOD0 low prohibits JTAG.
VDD
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•
•
TMS/BKPT
TDI/DSI
TRST/DSCLK
TCK
Disabling IEEE Standard 1149.1 Operation
TDI/DSI
TMS/BKPT
TRST/DSCLK
TCK
19-11