MCF5307AI90B Freescale Semiconductor, MCF5307AI90B Datasheet - Page 282

• Manufacturer Part Number: MCF5307AI90B
• Description: IC MPU 32BIT COLDF 90MHZ 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307AI90B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 90MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 90 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 90MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: FQFP
• Program Memory Size: 8KB
• Cpu Speed: 90MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

DMA Controller Module Programming Model
Any operation involving the DMA module follows the same three steps:
12.4 DMA Controller Module Programming Model
This section describes each internal register and its bit assignment. Note that there is no way
to prevent a write to a control register during a DMA transfer. Table 12-2 shows the
mapping of DMA controller registers. Note the differences for the byte count registers
depending on the value of MPARK[BCR24BIT].
12-4
1. Channel initialization—Channel registers are loaded with control information,
2. Data transfer—The DMA accepts requests for operand transfers and provides
3. Channel termination—Occurs after the operation is finished, either successfully or
address pointers, and a byte-transfer count.
addressing and bus control for the transfers.
due to an error. The channel indicates the operation status in the channel’s DSR,
described in Section 12.4.5, “DMA Status Registers (DSR0–DSR3).”
Write:
Read:
Freescale Semiconductor, Inc.
Figure 12-3. Single-Address Transfers
Control Signals
Control Signals
Memory
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Memory
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MCF5307 User’s Manual
Data
Data
DMA
DMA
Control Signals
Control Signals
Peripheral
Peripheral