MCF5307AI90B Freescale Semiconductor, MCF5307AI90B Datasheet - Page 419

• Manufacturer Part Number: MCF5307AI90B
• Description: IC MPU 32BIT COLDF 90MHZ 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307AI90B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 90MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 90 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 90MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: FQFP
• Program Memory Size: 8KB
• Cpu Speed: 90MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

In Figure 18-31, the external device is bus master during C1 and C2. During C2, the
MCF5307 requests the external bus because of a pending internal transfer. On C3, the
external releases mastership and the external arbiter grants the bus to the MCF5307 by
asserting BG. At this point, an internal is access pending so the MCF5307 asserts BD
during C4 and begins the access. Thus, the MCF5307 becomes the explicit bus master. Also
during C4, the external arbiter removes the grant from the MCF5307 by negating BG.
Because the MCF5307 is bus master, it continues to assert BD until the current transfer
completes. Because BG is negated, the MCF5307 negates BD during C9 and three-states
the external bus, thereby passing mastership to an external device.
The MCF5307 can assert BR to signal the external arbiter that it needs the bus. However,
there is no guarantee that when the bus is granted to the MCF5307 that a bus cycle will be
performed. At best, BR must be used as a status output that indicates when the MCF5307
needs the bus, but not as an indication that the MCF5307 is in a certain bus arbitration state.
Figure 18-32 is a high-level state diagram for MCF5307 bus arbitration protocol.
Table 18-6 describes the four states shown in Figure 18-32.
SIZ[1:0], TM[2:0]
A[31:0], TT[1:0]
BCLKO
D[31:0]
R/W
TIP
BG
BR
BD
TS
AS
TA
C1
Figure 18-31. Three-Wire Bus Arbitration
External
Master
Freescale Semiconductor, Inc.
C2
For More Information On This Product,
Chapter 18. Bus Operation
C3
Go to: www.freescale.com
C4
C5
General Operation of External Master Transfers
C6
MCF5307
C7
C8
C9
18-31