MCF5307AI90B Freescale Semiconductor, MCF5307AI90B Datasheet - Page 374

• Manufacturer Part Number: MCF5307AI90B
• Description: IC MPU 32BIT COLDF 90MHZ 208FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF530xr

Specifications of MCF5307AI90B

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 90MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, POR, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 90 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 90MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: FQFP
• Program Memory Size: 8KB
• Cpu Speed: 90MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

MCF5307 Bus Signals
external master access. This condition is indicated by the AM bit in the chip-select mask
register (CSMR) being cleared. See Chapter 10, “Chip-Select Module.”
17.2.8 Transfer In Progress (TIP/PP7)
The TIP/PP7 pin is programmed in the PAR to serve as the transfer-in-progress output or
as a parallel port bits. The TIP output is asserted indicating a bus transfer is in progress. It
is negated during idle bus cycles if the bus is still granted to the processor. It is three-stated
for external master accesses. Note that TIP is held asserted on back-to-back bus cycles.
17.2.9 Transfer Type (TT[1:0]/PP[1:0])
The TT[1:0]/PP[1:0] pins are programmed in the PAR to serve as the transfer type outputs
or as two parallel port bits. When the MCF5307 is bus master and TT[1:0] are enabled,
these signals are driven as outputs only. If an external master owns the bus and TT[1:0] are
enabled, these pins are three-stated by the MCF5307 and can be driven by the external
master. Table 17-5 shows the definition of the encodings.
17.2.10 Transfer Modifier (TM[2:0]/PP[4:2])
The TM[2:0]/PP[4:2] pins are programmed in the PAR to serve as the transfer modifier
outputs or as three parallel port bits. These outputs provide supplemental information for
each transfer type; see Table 17-6 through Table 17-10.
When the MCF5307 is the bus master and TM[2:0] are enabled, these signals are driven as
outputs only. If an external device is bus master and TM[2:0] are enabled, these pins are
three-stated by the MCF5307 and can be driven by the external master.
17-10
Table 17-6. TM[2:0] Encodings for TT = 00 (Normal Access)
Table 17-5. Bus Cycle Transfer Type Encoding
TT[1:0]
00
01
10
11
Freescale Semiconductor, Inc.
For More Information On This Product,
Normal access
DMA access
Emulator access
CPU space or interrupt acknowledge
011–100
TM[2:0]
000
001
010
101
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MCF5307 User’s Manual
Cache push access
User data access
User code access
Reserved
Supervisor data access
Transfer Modifier
Transfer Type